Paul A. Bunce

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory array having power consumption characteristics
- Patent number 11,150,818
- Issue date Oct 19, 2021
- International Business Machines Corporation
- Russell Hayes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise injection circuit
- Patent number 11,067,627
- Issue date Jul 20, 2021
- International Business Machines Corporation
- Brian James Yavoich
- G01 - MEASURING TESTING
Information Patent Grant
Random-access memory array memory cell selection
- Patent number 10,978,140
- Issue date Apr 13, 2021
- International Business Machines Corporation
- Paul Alan Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Fine-grained programmable delay and pulse shaping circuit
- Patent number 10,840,895
- Issue date Nov 17, 2020
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic decode circuit with active glitch control
- Patent number 10,367,507
- Issue date Jul 30, 2019
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic decode circuit with active glitch control method
- Patent number 10,320,388
- Issue date Jun 11, 2019
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic decode circuit with active glitch control method
- Patent number 10,312,915
- Issue date Jun 4, 2019
- International Business Machines Corporation
- Paul Alan Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic decode circuit with delayed precharge
- Patent number 10,312,916
- Issue date Jun 4, 2019
- International Business Machines Corporation
- Paul Alan Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic decode circuit with active glitch control
- Patent number 10,224,933
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual mode operation having power saving and active modes in a stack...
- Patent number 9,997,218
- Issue date Jun 12, 2018
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Cache array with reduced power consumption
- Patent number 9,977,485
- Issue date May 22, 2018
- International Business Machines Corporation
- Paul A. Bunce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache array with reduced power consumption
- Patent number 9,971,394
- Issue date May 15, 2018
- International Business Machines Corporation
- Paul A. Bunce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic decode circuit with active glitch control
- Patent number 9,966,958
- Issue date May 8, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Managing semiconductor memory array leakage current
- Patent number 9,792,967
- Issue date Oct 17, 2017
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual mode operation having power saving and active modes in a stack...
- Patent number 9,786,339
- Issue date Oct 10, 2017
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing semiconductor memory array leakage current
- Patent number 9,761,289
- Issue date Sep 12, 2017
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic decode circuit with active glitch control
- Patent number 9,742,408
- Issue date Aug 22, 2017
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Incorporating bit write capability with column interleave write ena...
- Patent number 9,583,211
- Issue date Feb 28, 2017
- International Business Machines Coproration
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
High frequency write through memory device
- Patent number 9,355,692
- Issue date May 31, 2016
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Write/read priority blocking scheme using parallel static address d...
- Patent number 9,281,024
- Issue date Mar 8, 2016
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Write/read priority blocking scheme using parallel static address d...
- Patent number 9,281,025
- Issue date Mar 8, 2016
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM supply voltage global bitline precharge pulse
- Patent number 9,070,433
- Issue date Jun 30, 2015
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Increasing memory operating frequency
- Patent number 8,861,284
- Issue date Oct 14, 2014
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Port enable signal generation for gating a memory array device output
- Patent number 8,599,642
- Issue date Dec 3, 2013
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Jam latch for latching memory array output data
- Patent number 8,351,278
- Issue date Jan 8, 2013
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Internal bypassing of memory array devices
- Patent number 8,345,497
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Split voltage level restore and evaluate clock signals for memory a...
- Patent number 8,345,490
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable control clock circuit including scan mode
- Patent number 8,299,833
- Issue date Oct 30, 2012
- International Business Machines Corporation
- Paul A. Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Write control method for a memory array configured with multiple me...
- Patent number 7,688,650
- Issue date Mar 30, 2010
- International Business Machines Corporation
- John D. Davis
- G11 - INFORMATION STORAGE
Information Patent Grant
Write control circuitry and method for a memory array configured wi...
- Patent number 7,471,590
- Issue date Dec 30, 2008
- International Business Machines Corporation
- John D. Davis
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
NOISE INJECTION CIRCUIT
- Publication number 20210072313
- Publication date Mar 11, 2021
- International Business Machines Corporation
- BRIAN JAMES YAVOICH
- G01 - MEASURING TESTING
Information Patent Application
RANDOM-ACCESS MEMORY ARRAY MEMORY CELL SELECTION
- Publication number 20210074351
- Publication date Mar 11, 2021
- International Business Machines Corporation
- PAUL ALAN BUNCE
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY HAVING POWER CONSUMPTION CHARACTERISTICS
- Publication number 20210072905
- Publication date Mar 11, 2021
- International Business Machines Corporation
- RUSSELL HAYES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL
- Publication number 20180367145
- Publication date Dec 20, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL METHOD
- Publication number 20180323786
- Publication date Nov 8, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC DECODE CIRCUIT WITH DELAYED PRECHARGE
- Publication number 20180323787
- Publication date Nov 8, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL Method
- Publication number 20180316354
- Publication date Nov 1, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL
- Publication number 20180091152
- Publication date Mar 29, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL
- Publication number 20180091153
- Publication date Mar 29, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACK...
- Publication number 20180005674
- Publication date Jan 4, 2018
- International Business Machines Corporation
- PAUL A. BUNCE
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACK...
- Publication number 20170243619
- Publication date Aug 24, 2017
- International Business Machines Corporation
- PAUL A. BUNCE
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS D...
- Publication number 20150302902
- Publication date Oct 22, 2015
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS D...
- Publication number 20150302908
- Publication date Oct 22, 2015
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
CACHE ARRAY WITH REDUCED POWER CONSUMPTION
- Publication number 20150019890
- Publication date Jan 15, 2015
- International Business Machines Corporation
- Paul A. Bunce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH FREQUENCY MEMORY
- Publication number 20140078835
- Publication date Mar 20, 2014
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
CACHE ARRAY WITH REDUCED POWER CONSUMPTION
- Publication number 20140082390
- Publication date Mar 20, 2014
- International Business Machines Corporation
- Paul A. Bunce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASING MEMORY OPERATING FREQUENCY
- Publication number 20140078833
- Publication date Mar 20, 2014
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT
- Publication number 20110320851
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Paul A. Bunce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JAM LATCH FOR LATCHING MEMORY ARRAY OUTPUT DATA
- Publication number 20110317496
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
SPLIT VOLTAGE LEVEL RESTORE AND EVALUATE CLOCK SIGNALS FOR MEMORY A...
- Publication number 20110317499
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
INTERNAL BYPASSING OF MEMORY ARRAY DEVICES
- Publication number 20110317505
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE CONTROL CLOCK CIRCUIT INCLUDING SCAN MODE
- Publication number 20110304370
- Publication date Dec 15, 2011
- International Business Machines Corporation
- Paul A. Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
WRITE CONTROL METHOD FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE ME...
- Publication number 20080247245
- Publication date Oct 9, 2008
- International Business Machines Corporation
- John D. Davis
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCK CONTROL METHOD AND APPARATUS FOR A MEMORY ARRAY
- Publication number 20080028255
- Publication date Jan 31, 2008
- International Business Machines Corporation
- James W. Dawson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE CONTROL CIRCUITRY AND METHOD FOR A MEMORY ARRAY CONFIGURED WI...
- Publication number 20070237020
- Publication date Oct 11, 2007
- International Business Machines Corporation
- John D. Davis
- G11 - INFORMATION STORAGE
Information Patent Application
Method for enabling scan of defective ram prior to repair
- Publication number 20070033459
- Publication date Feb 8, 2007
- International Business Machines Corporation
- Paul A. Bunce
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT AND METHOD FOR WRITING A BINARY VALUE TO A MEMORY CELL
- Publication number 20060181954
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for address generation
- Publication number 20060181951
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
Programmable analog control of a bitline evaluation circuit
- Publication number 20060181952
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
Method and circuit for implementing array bypass operations without...
- Publication number 20060179382
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Paul A. Bunce
- G06 - COMPUTING CALCULATING COUNTING

Paul A. Bunce

Person

Patents Grantslast 30 patents

Memory array having power consumption characteristics

Noise injection circuit

Random-access memory array memory cell selection

Fine-grained programmable delay and pulse shaping circuit

Dynamic decode circuit with active glitch control

Dynamic decode circuit with active glitch control method

Dynamic decode circuit with active glitch control method

Dynamic decode circuit with delayed precharge

Dynamic decode circuit with active glitch control

Dual mode operation having power saving and active modes in a stack...

Cache array with reduced power consumption

Cache array with reduced power consumption

Dynamic decode circuit with active glitch control

Managing semiconductor memory array leakage current

Dual mode operation having power saving and active modes in a stack...

Managing semiconductor memory array leakage current

Dynamic decode circuit with active glitch control

Incorporating bit write capability with column interleave write ena...

High frequency write through memory device

Write/read priority blocking scheme using parallel static address d...

Write/read priority blocking scheme using parallel static address d...

SRAM supply voltage global bitline precharge pulse

Increasing memory operating frequency

Port enable signal generation for gating a memory array device output

Jam latch for latching memory array output data

Internal bypassing of memory array devices

Split voltage level restore and evaluate clock signals for memory a...

Programmable control clock circuit including scan mode

Write control method for a memory array configured with multiple me...

Write control circuitry and method for a memory array configured wi...

Patents Applicationslast 30 patents

NOISE INJECTION CIRCUIT

RANDOM-ACCESS MEMORY ARRAY MEMORY CELL SELECTION

MEMORY ARRAY HAVING POWER CONSUMPTION CHARACTERISTICS

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL METHOD

DYNAMIC DECODE CIRCUIT WITH DELAYED PRECHARGE

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL Method

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL

DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACK...

DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACK...

WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS D...

WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS D...

CACHE ARRAY WITH REDUCED POWER CONSUMPTION

HIGH FREQUENCY MEMORY

CACHE ARRAY WITH REDUCED POWER CONSUMPTION

INCREASING MEMORY OPERATING FREQUENCY

PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT

JAM LATCH FOR LATCHING MEMORY ARRAY OUTPUT DATA

SPLIT VOLTAGE LEVEL RESTORE AND EVALUATE CLOCK SIGNALS FOR MEMORY A...

INTERNAL BYPASSING OF MEMORY ARRAY DEVICES

PROGRAMMABLE CONTROL CLOCK CIRCUIT INCLUDING SCAN MODE

WRITE CONTROL METHOD FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE ME...

CLOCK CONTROL METHOD AND APPARATUS FOR A MEMORY ARRAY

WRITE CONTROL CIRCUITRY AND METHOD FOR A MEMORY ARRAY CONFIGURED WI...

Method for enabling scan of defective ram prior to repair

CIRCUIT AND METHOD FOR WRITING A BINARY VALUE TO A MEMORY CELL

Method and apparatus for address generation

Programmable analog control of a bitline evaluation circuit

Method and circuit for implementing array bypass operations without...