Paul D. Agnello

Person

Wappingers Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Relaxed low-defect SGOI for strained SI CMOS applications
- Patent number 8,227,792
- Issue date Jul 24, 2012
- International Business Machines Corporation
- Paul D. Agnello
- C30 - CRYSTAL GROWTH
Information Patent Grant
Multiple crystallographic orientation semiconductor structures
- Patent number 7,993,990
- Issue date Aug 9, 2011
- International Business Machines Corporation
- Shreesh Narasimha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple crystallographic orientation semiconductor structures
- Patent number 7,696,573
- Issue date Apr 13, 2010
- International Business Machines Corporation
- Shreesh Narasimha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Preventing cavitation in high aspect ratio dielectric regions of se...
- Patent number 7,683,434
- Issue date Mar 23, 2010
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Preventing cavitation in high aspect ratio dielectric regions of se...
- Patent number 7,459,384
- Issue date Dec 2, 2008
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating semiconductor side wall fin
- Patent number 7,361,556
- Issue date Apr 22, 2008
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Relaxed, low-defect SGOI for strained Si CMOS applications
- Patent number 7,358,166
- Issue date Apr 15, 2008
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating semiconductor side wall fin
- Patent number 7,265,417
- Issue date Sep 4, 2007
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating semiconductor side wall fin
- Patent number 7,163,864
- Issue date Jan 16, 2007
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double gate trench transistor
- Patent number 7,112,845
- Issue date Sep 26, 2006
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for controlling the interface roughness of cobalt disilicide
- Patent number 7,081,676
- Issue date Jul 25, 2006
- International Business Machines Corporation
- Paul David Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Relaxed, low-defect SGOI for strained Si CMOS applications
- Patent number 6,946,373
- Issue date Sep 20, 2005
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Salicide formation method
- Patent number 6,916,729
- Issue date Jul 12, 2005
- Infineon Technologies AG
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS device on ultrathin SOI with a deposited raised source/drain,...
- Patent number 6,891,228
- Issue date May 10, 2005
- International Business Machines Corporation
- Heemyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS device on ultrathin SOI with a deposited raised source/drain,...
- Patent number 6,828,630
- Issue date Dec 7, 2004
- International Business Machines Corporation
- Heemyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for controlling the interface roughness of cob...
- Patent number 6,809,030
- Issue date Oct 26, 2004
- International Business Machines Corporation
- Paul David Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip having both compact memory and high performance...
- Patent number 6,686,617
- Issue date Feb 3, 2004
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma treatment to enhance inorganic dielectric adhesion to copper
- Patent number 6,593,660
- Issue date Jul 15, 2003
- International Business Machines Corporation
- Leena P. Buchwalter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure of a dual/wrap-around gate field effect transi...
- Patent number 6,563,131
- Issue date May 13, 2003
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double gate trench transistor
- Patent number 6,472,258
- Issue date Oct 29, 2002
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for controlling the interface roughness of cob...
- Patent number 6,440,851
- Issue date Aug 27, 2002
- International Business Machines Corporation
- Paul David Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical trench-formed dual-gate FET device structure and method fo...
- Patent number 6,406,962
- Issue date Jun 18, 2002
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with abrupt source/drain extensions with contr...
- Patent number 6,407,436
- Issue date Jun 18, 2002
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double polysilicon process for providing single chip high performan...
- Patent number 6,287,913
- Issue date Sep 11, 2001
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating abrupt source/drain extensions with controll...
- Patent number 6,274,446
- Issue date Aug 14, 2001
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma treatment to enhance inorganic dielectric adhesion to copper
- Patent number 6,261,951
- Issue date Jul 17, 2001
- International Business Machines Corporation
- Leena P. Buchwalter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma treatment to enhance inorganic dielectric adhesion to copper
- Patent number 6,255,217
- Issue date Jul 3, 2001
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a capped gate conductor
- Patent number 5,897,349
- Issue date Apr 27, 1999
- International Business Machines Corporation
- Paul David Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tasin oxygen diffusion barrier in multilayer structures
- Patent number 5,796,166
- Issue date Aug 18, 1998
- IBM Corporation
- Paul David Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tasin oxygen diffusion barrier in multilayer structures
- Patent number 5,776,823
- Issue date Jul 7, 1998
- IBM Corporation
- Paul David Agnello
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES
- Publication number 20100197118
- Publication date Aug 5, 2010
- International Business Machines Corporation
- Shreesh Narasimha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES
- Publication number 20090108302
- Publication date Apr 30, 2009
- International Business Machines Corporation
- Shreesh Narasimha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SE...
- Publication number 20080303070
- Publication date Dec 11, 2008
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RELAXED LOW-DEFECT SGOI FOR STRAINED Si CMOS APPLICATIONS
- Publication number 20080135875
- Publication date Jun 12, 2008
- International Business Machines Corporation
- Paul D. Agnello
- C30 - CRYSTAL GROWTH
Information Patent Application
Method of fabricating semiconductor side wall fin
- Publication number 20070026617
- Publication date Feb 1, 2007
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Relaxed, low-defect SGOI for strained Si CMOS applications
- Publication number 20060030133
- Publication date Feb 9, 2006
- International Business Machines Corporation
- Paul D. Agnello
- C30 - CRYSTAL GROWTH
Information Patent Application
PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SE...
- Publication number 20050287798
- Publication date Dec 29, 2005
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO PRODUCE TRANSISTOR HAVING REDUCED GATE HEIGHT
- Publication number 20050048732
- Publication date Mar 3, 2005
- International Business Machines Corporation
- Heemyoung Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS device on ultrathin SOI with a deposited raised source/drain,...
- Publication number 20050040465
- Publication date Feb 24, 2005
- Heemyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating semiconductor side wall fin
- Publication number 20050001216
- Publication date Jan 6, 2005
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Salicide formation method
- Publication number 20040203229
- Publication date Oct 14, 2004
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS device on ultrathin SOI with a deposited raised source/drain,...
- Publication number 20040129979
- Publication date Jul 8, 2004
- International Business Machines Corporation
- Heemyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Relaxed, low-defect SGOI for strained Si CMOS applications
- Publication number 20040094763
- Publication date May 20, 2004
- International Business Machines Corporation
- Paul D. Agnello
- C30 - CRYSTAL GROWTH
Information Patent Application
Method and structure for controlling the interface roughness of cob...
- Publication number 20040087160
- Publication date May 6, 2004
- International Business Machines Corporation
- Paul David Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PARTIALLY REMOVABLE SPACER WITH SALICIDE FORMATION
- Publication number 20030042551
- Publication date Mar 6, 2003
- PAUL D. AGNELLO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and structure for controlling the interface roughness of cob...
- Publication number 20020182836
- Publication date Dec 5, 2002
- International Business Machines Corporation
- Paul David Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structures and methods to minimize plasma charging damage in silico...
- Publication number 20020142526
- Publication date Oct 3, 2002
- International Business Machines Corporation
- Mukesh Khare
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Double gate trench transistor
- Publication number 20020140039
- Publication date Oct 3, 2002
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating abrupt source/drain extensions with controll...
- Publication number 20020025639
- Publication date Feb 28, 2002
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Plasma treatment to enhance inorganic dielectric adhesion to copper
- Publication number 20010053591
- Publication date Dec 20, 2001
- International Business Machines Corporation
- Leena P. Buchwalter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor chip having both compact memory and high performance...
- Publication number 20010031535
- Publication date Oct 18, 2001
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS

Paul D. Agnello

Person

Patents Grantslast 30 patents

Relaxed low-defect SGOI for strained SI CMOS applications

Multiple crystallographic orientation semiconductor structures

Multiple crystallographic orientation semiconductor structures

Preventing cavitation in high aspect ratio dielectric regions of se...

Preventing cavitation in high aspect ratio dielectric regions of se...

Method of fabricating semiconductor side wall fin

Relaxed, low-defect SGOI for strained Si CMOS applications

Method of fabricating semiconductor side wall fin

Method of fabricating semiconductor side wall fin

Double gate trench transistor

Structure for controlling the interface roughness of cobalt disilicide

Relaxed, low-defect SGOI for strained Si CMOS applications

Salicide formation method

CMOS device on ultrathin SOI with a deposited raised source/drain,...

CMOS device on ultrathin SOI with a deposited raised source/drain,...

Method and structure for controlling the interface roughness of cob...

Semiconductor chip having both compact memory and high performance...

Plasma treatment to enhance inorganic dielectric adhesion to copper

Method and structure of a dual/wrap-around gate field effect transi...

Double gate trench transistor

Method and structure for controlling the interface roughness of cob...

Vertical trench-formed dual-gate FET device structure and method fo...

Semiconductor device with abrupt source/drain extensions with contr...

Double polysilicon process for providing single chip high performan...

Method for fabricating abrupt source/drain extensions with controll...

Plasma treatment to enhance inorganic dielectric adhesion to copper

Plasma treatment to enhance inorganic dielectric adhesion to copper

Method for fabricating a capped gate conductor

Tasin oxygen diffusion barrier in multilayer structures

Tasin oxygen diffusion barrier in multilayer structures

Patents Applicationslast 30 patents

MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES

MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES

PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SE...

RELAXED LOW-DEFECT SGOI FOR STRAINED Si CMOS APPLICATIONS

Method of fabricating semiconductor side wall fin

Relaxed, low-defect SGOI for strained Si CMOS applications

PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SE...

METHOD TO PRODUCE TRANSISTOR HAVING REDUCED GATE HEIGHT

CMOS device on ultrathin SOI with a deposited raised source/drain,...

Method of fabricating semiconductor side wall fin

Salicide formation method

CMOS device on ultrathin SOI with a deposited raised source/drain,...

Relaxed, low-defect SGOI for strained Si CMOS applications

Method and structure for controlling the interface roughness of cob...

PARTIALLY REMOVABLE SPACER WITH SALICIDE FORMATION

Method and structure for controlling the interface roughness of cob...

Structures and methods to minimize plasma charging damage in silico...

Double gate trench transistor

Method for fabricating abrupt source/drain extensions with controll...

Plasma treatment to enhance inorganic dielectric adhesion to copper

Semiconductor chip having both compact memory and high performance...