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Paul D. Ta
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San Jose, CA, US
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last 30 patents
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Patent Grant
High speed phase aligner with jitter removal
Patent number
5,608,357
Issue date
Mar 4, 1997
VLSI Technology, Inc.
Paul Ta
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Low noise low voltage phase lock loop
Patent number
5,523,723
Issue date
Jun 4, 1996
VLSI Technology, Inc.
Christopher G. Arcus
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Very low noise, wide frequency range phase lock loop
Patent number
5,515,012
Issue date
May 7, 1996
VLSI Technology, Inc.
Bharat Bhushan
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
High-speed low-power CMOS PECL I/O transmitter
Patent number
5,495,184
Issue date
Feb 27, 1996
VLSI Technology, Inc.
Andre P. Des Rosiers
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Digital-to-analog converter and bias compensator therefor
Patent number
5,293,166
Issue date
Mar 8, 1994
VLSI Technology, Inc.
Paul D. Ta
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Differential output buffer with feedback
Patent number
5,227,673
Issue date
Jul 13, 1993
VLSI Technology, Inc.
Paul D. Ta
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Precharged buffer with reduced output voltage swing
Patent number
5,134,316
Issue date
Jul 28, 1992
VLSI Technology, Inc.
Paul D. Ta
G11 - INFORMATION STORAGE
Information
Patent Grant
Differential amplifier with enhanced slew rate
Patent number
5,070,307
Issue date
Dec 3, 1991
VLSI Technology, Inc.
Paul D. Ta
H03 - BASIC ELECTRONIC CIRCUITRY