Paul J. Steffan

Person

Elk Grove, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Image processing in integrated circuit technology development
- Patent number 7,590,309
- Issue date Sep 15, 2009
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for correlating semiconductor process data wit...
- Patent number 7,263,451
- Issue date Aug 28, 2007
- Advanced Micro Devices, Inc.
- Jeffrey P. Erhardt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predicting defect future effects in integrated circuit technology d...
- Patent number 7,251,793
- Issue date Jul 31, 2007
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure and method for failure analysis of small contacts in...
- Patent number 7,135,879
- Issue date Nov 14, 2006
- Advanced Micro Devices, Inc.
- David C. Newbury
- G01 - MEASURING TESTING
Information Patent Grant
Wafer level global bitmap characterization in integrated circuit te...
- Patent number 7,137,085
- Issue date Nov 14, 2006
- Advanced Micro Devices, Inc.
- John J. Wang
- G01 - MEASURING TESTING
Information Patent Grant
Characterizing distribution signatures in integrated circuit techno...
- Patent number 7,099,789
- Issue date Aug 29, 2006
- Advanced Micro Devices, Inc.
- Franklyn Shihyu Wu
- G01 - MEASURING TESTING
Information Patent Grant
Testing multiple levels in integrated circuit technology development
- Patent number 6,875,560
- Issue date Apr 5, 2005
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- G01 - MEASURING TESTING
Information Patent Grant
Methods to form reduced dimension bit-line isolation in the manufac...
- Patent number 6,596,591
- Issue date Jul 22, 2003
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Controlled gate length and gate profile semiconductor device and ma...
- Patent number 6,524,916
- Issue date Feb 25, 2003
- Advanced Micro Devices, Inc.
- Thomas C. Scholer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composition based association engine for image archival systems
- Patent number 6,512,842
- Issue date Jan 28, 2003
- Advanced Micro Devices
- Paul J. Steffan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of forming low resistance reduced channel length transistors
- Patent number 6,506,639
- Issue date Jan 14, 2003
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Overlay radius offset shift engine
- Patent number 6,468,815
- Issue date Oct 22, 2002
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Automatic defect resizing tool
- Patent number 6,463,171
- Issue date Oct 8, 2002
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor with increased gate coupling coefficient
- Patent number 6,448,606
- Issue date Sep 10, 2002
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Controlled gate length and gate profile semiconductor device
- Patent number 6,433,371
- Issue date Aug 13, 2002
- Advanced Micro Devices, Inc.
- Thomas C. Scholer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recipe management database system
- Patent number 6,430,572
- Issue date Aug 6, 2002
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer generated recipe selector utilizing defect file information
- Patent number 6,424,881
- Issue date Jul 23, 2002
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ADC based in-situ destructive analysis selection and methodology th...
- Patent number 6,423,557
- Issue date Jul 23, 2002
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Automatic defect classification system based variable sampling plan
- Patent number 6,421,574
- Issue date Jul 16, 2002
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process control using ideal die data in an optical comparator scann...
- Patent number 6,395,567
- Issue date May 28, 2002
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- G01 - MEASURING TESTING
Information Patent Grant
Automatic defect classification comparator die selection system
- Patent number 6,377,898
- Issue date Apr 23, 2002
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simplified graded LDD transistor using controlled polysilicon gate...
- Patent number 6,350,639
- Issue date Feb 26, 2002
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In line yield prediction using ADC determined kill ratios die healt...
- Patent number 6,338,001
- Issue date Jan 8, 2002
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Global cluster pre-classification methodology
- Patent number 6,303,394
- Issue date Oct 16, 2001
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Automatic method to eliminate first-wafer effect
- Patent number 6,291,252
- Issue date Sep 18, 2001
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electroless plated semiconductor vias and channels
- Patent number 6,291,332
- Issue date Sep 18, 2001
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of defining copper seed layer for selective electroless plat...
- Patent number 6,287,968
- Issue date Sep 11, 2001
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating graded LDD transistor using controlled polys...
- Patent number 6,287,922
- Issue date Sep 11, 2001
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Location dependent automatic defect classification
- Patent number 6,284,553
- Issue date Sep 4, 2001
- Advanced Micro Devices, Inc.
- Paul J. Steffan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simplified graded LDD transistor using controlled polysilicon gate...
- Patent number 6,274,443
- Issue date Aug 14, 2001
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS

Paul J. Steffan

Person

Patents Grantslast 30 patents

Image processing in integrated circuit technology development

Method and apparatus for correlating semiconductor process data wit...

Predicting defect future effects in integrated circuit technology d...

Test structure and method for failure analysis of small contacts in...

Wafer level global bitmap characterization in integrated circuit te...

Characterizing distribution signatures in integrated circuit techno...

Testing multiple levels in integrated circuit technology development

Methods to form reduced dimension bit-line isolation in the manufac...

Controlled gate length and gate profile semiconductor device and ma...

Composition based association engine for image archival systems

Method of forming low resistance reduced channel length transistors

Overlay radius offset shift engine

Automatic defect resizing tool

Semiconductor with increased gate coupling coefficient

Controlled gate length and gate profile semiconductor device

Recipe management database system

Computer generated recipe selector utilizing defect file information

ADC based in-situ destructive analysis selection and methodology th...

Automatic defect classification system based variable sampling plan

Process control using ideal die data in an optical comparator scann...

Automatic defect classification comparator die selection system

Simplified graded LDD transistor using controlled polysilicon gate...

In line yield prediction using ADC determined kill ratios die healt...

Global cluster pre-classification methodology

Automatic method to eliminate first-wafer effect

Electroless plated semiconductor vias and channels

Method of defining copper seed layer for selective electroless plat...

Method for fabricating graded LDD transistor using controlled polys...

Location dependent automatic defect classification

Simplified graded LDD transistor using controlled polysilicon gate...