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Paul Jaynes
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Attleboro, MA, US
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Patents Grants
last 30 patents
Information
Patent Grant
Chip package sealing method
Patent number
7,972,901
Issue date
Jul 5, 2011
Foster-Miller, Inc.
Brian Farrell
Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information
Patent Grant
Electronic and optoelectronic component packaging technique
Patent number
7,476,566
Issue date
Jan 13, 2009
Foster-Miller, Inc.
Brian Farrell
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Chip package sealing method
Patent number
6,977,187
Issue date
Dec 20, 2005
Foster-Miller, Inc.
Brian Farrell
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Electronic and optoelectronic component packaging technique
Patent number
6,952,046
Issue date
Oct 4, 2005
Foster-Miller, Inc.
Brian Farrell
H01 - BASIC ELECTRIC ELEMENTS
Patents Applications
last 30 patents
Information
Patent Application
Electronic and optoelectronic component packaging technique
Publication number
20050260797
Publication date
Nov 24, 2005
Brian Farrell
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
Chip package sealing method
Publication number
20050189332
Publication date
Sep 1, 2005
Brian Farrell
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
Chip package sealing method
Publication number
20040010910
Publication date
Jan 22, 2004
Brian Farrell
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
Electronic and optoelectronic component packaging technique
Publication number
20040012083
Publication date
Jan 22, 2004
Brian Farrell
H01 - BASIC ELECTRIC ELEMENTS