Paul T. Gutwin

Person

Williston, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Inter-tier power delivery network (PDN) for dense gate-on-gate 3D l...
- Patent number 12,176,293
- Issue date Dec 24, 2024
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated high efficiency transistor cooling
- Patent number 12,051,638
- Issue date Jul 30, 2024
- Tokyo Electron Limited
- Daniel Chanemougame
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inter-level handshake for dense 3D logic integration
- Patent number 12,002,862
- Issue date Jun 4, 2024
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power-tap pass-through to connect a buried power rail to front-side...
- Patent number 11,961,802
- Issue date Apr 16, 2024
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double cross-couple for two-row flip-flop using CFET
- Patent number 11,923,364
- Issue date Mar 5, 2024
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-tier backside power delivery network for dense gate-on-gate 3...
- Patent number 11,830,852
- Issue date Nov 28, 2023
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of 3D logic fabrication to sequentially decrease processing...
- Patent number 11,764,113
- Issue date Sep 19, 2023
- Tokyo Electron Limited
- Jeffrey Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional semiconductor device
- Patent number 11,764,266
- Issue date Sep 19, 2023
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional memory cell structure
- Patent number 11,723,187
- Issue date Aug 8, 2023
- Tokyo Electron Limited
- Paul Gutwin
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated high efficiency gate on gate cooling
- Patent number 11,581,242
- Issue date Feb 14, 2023
- Tokyo Electron Limited
- Daniel Chanemougame
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked three-dimensional field-effect transistors
- Patent number 11,532,708
- Issue date Dec 20, 2022
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Variable detail automatic invocation of transistor level timing for...
- Patent number 6,829,755
- Issue date Dec 7, 2004
- International Business Machines Corporation
- Paul T. Gutwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for hiding refresh cycles in a dynamic type conte...
- Patent number 6,671,218
- Issue date Dec 30, 2003
- International Business Machines Corporation
- Paul Gutwin
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of partitioning large transistor design to facilitate transi...
- Patent number 6,588,000
- Issue date Jul 1, 2003
- International Business Machines Corporation
- Paul T. Gutwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for allocating data and instructions within a...
- Patent number 6,532,520
- Issue date Mar 11, 2003
- International Business Machines Corporation
- Alvar A. Dean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for improving caching within a processor system
- Patent number 6,449,693
- Issue date Sep 10, 2002
- International Business Machines Corporation
- John W. Goetz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor system requests burstable access to noncacheable mem...
- Patent number 6,178,467
- Issue date Jan 23, 2001
- International Business Machines Corporation
- Marc R. Faucher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit delay abstraction tool
- Patent number 5,796,621
- Issue date Aug 18, 1998
- International Business Machines Corporation
- Peter E. Dudley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for measuring pulse distortion
- Patent number 5,239,481
- Issue date Aug 24, 1993
- International Business Machines Corporation
- Thomas W. Brooks
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED HIGH EFFICIENCY TRANSISTOR COOLING
- Publication number 20240347422
- Publication date Oct 17, 2024
- TOKYO ELECTRON LIMITED
- Daniel CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BEOL CONTACT METALS FOR 2D TRANSISTORS
- Publication number 20240222461
- Publication date Jul 4, 2024
- Intel Corporation
- Ande Kitamura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wiring in Diffusion Breaks in an Integrated Circuit
- Publication number 20230223404
- Publication date Jul 13, 2023
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
- Publication number 20230100332
- Publication date Mar 30, 2023
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TAPERED DEVICE FOR LATERAL GATE ALL AROUND DEVICES
- Publication number 20230078381
- Publication date Mar 16, 2023
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED METHOD FOR VERTICAL RECESS FOR 3D DEVICE INTEGRATION
- Publication number 20230036597
- Publication date Feb 2, 2023
- TOKYO ELECTRON LIMITED
- Jeffrey SMITH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INDEPENDENT GATE CONTACTS FOR CFET
- Publication number 20230017350
- Publication date Jan 19, 2023
- TOKYO ELECTRON LIMITED
- Daniel CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE HAVING STACKED GATES AND METHOD OF MANUFACT...
- Publication number 20220416048
- Publication date Dec 29, 2022
- TOKYO ELECTRON LIMITED
- Jeffrey SMITH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INVERTED CROSS-COUPLE FOR TOP-TIER FET FOR MULTI-TIER GATE-ON-GATE 3DI
- Publication number 20220367461
- Publication date Nov 17, 2022
- TOKYO ELECTRON LIMITED
- Daniel CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY CELL STRUCTURE
- Publication number 20220302121
- Publication date Sep 22, 2022
- TOKYO ELECTRON LIMITED
- Paul GUTWIN
- G11 - INFORMATION STORAGE
Information Patent Application
INVERTED TOP-TIER FET FOR MULTI-TIER GATE-ON-GATE 3-DIMENSION INTEG...
- Publication number 20220271033
- Publication date Aug 25, 2022
- Daniel CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED HIGH EFFICIENCY GATE ON GATE COOLING
- Publication number 20220223497
- Publication date Jul 14, 2022
- TOKYO ELECTRON LIMITED
- Daniel CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED HIGH EFFICIENCY TRANSISTOR COOLING
- Publication number 20220223496
- Publication date Jul 14, 2022
- TOKYO ELECTRON LIMITED
- Daniel CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER-TAP PASS-THROUGH TO CONNECT A BURIED POWER RAIL TO FRONT-SIDE...
- Publication number 20220181258
- Publication date Jun 9, 2022
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
- Publication number 20220181441
- Publication date Jun 9, 2022
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTER-TIER POWER DELIVERY NETWORK (PDN) FOR DENSE GATE-ON-GATE 3D L...
- Publication number 20220181263
- Publication date Jun 9, 2022
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-TIER BACKSIDE POWER DELIVERY NETWORK FOR DENSE GATE-ON-GATE 3...
- Publication number 20220181300
- Publication date Jun 9, 2022
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERDIGITATED DEVICE STACK
- Publication number 20220181318
- Publication date Jun 9, 2022
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTER-LEVEL HANDSHAKE FOR DENSE 3D LOGIC INTEGRATION
- Publication number 20220181453
- Publication date Jun 9, 2022
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE CROSS-COUPLE FOR TWO-ROW FLIP-FLOP USING CFET
- Publication number 20220181322
- Publication date Jun 9, 2022
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF 3D LOGIC FABRICATION TO SEQUENTIALLY DECREASE PROCESSING...
- Publication number 20220122892
- Publication date Apr 21, 2022
- TOKYO ELECTRON LIMITED
- Jeffrey SMITH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and method for hiding refresh cycles in a dynamic type conte...
- Publication number 20030112686
- Publication date Jun 19, 2003
- International Business Machines Corporation
- Paul Gutwin
- G11 - INFORMATION STORAGE
Information Patent Application
VARIABLE DETAIL AUTOMATIC INVOCATION OF TRANSISTOR LEVEL TIMING FOR...
- Publication number 20030037306
- Publication date Feb 20, 2003
- International Business Machines Corporation
- Paul T. Gutwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of partitioning large transistor design to facilitate transi...
- Publication number 20030033583
- Publication date Feb 13, 2003
- Paul T. Gutwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Directed least recently used cache replacement method
- Publication number 20020152361
- Publication date Oct 17, 2002
- International Business Machines Corporation
- Alvar A. Dean
- G06 - COMPUTING CALCULATING COUNTING

Paul T. Gutwin

Person

Patents Grantslast 30 patents

Inter-tier power delivery network (PDN) for dense gate-on-gate 3D l...

Integrated high efficiency transistor cooling

Inter-level handshake for dense 3D logic integration

Power-tap pass-through to connect a buried power rail to front-side...

Double cross-couple for two-row flip-flop using CFET

Multi-tier backside power delivery network for dense gate-on-gate 3...

Method of 3D logic fabrication to sequentially decrease processing...

Three-dimensional semiconductor device

Three-dimensional memory cell structure

Integrated high efficiency gate on gate cooling

Stacked three-dimensional field-effect transistors

Variable detail automatic invocation of transistor level timing for...

System and method for hiding refresh cycles in a dynamic type conte...

Method of partitioning large transistor design to facilitate transi...

Method and apparatus for allocating data and instructions within a...

Method and apparatus for improving caching within a processor system

Microprocessor system requests burstable access to noncacheable mem...

Circuit delay abstraction tool

Method for measuring pulse distortion

Patents Applicationslast 30 patents

INTEGRATED HIGH EFFICIENCY TRANSISTOR COOLING

BEOL CONTACT METALS FOR 2D TRANSISTORS

Wiring in Diffusion Breaks in an Integrated Circuit

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

TAPERED DEVICE FOR LATERAL GATE ALL AROUND DEVICES

SELF-ALIGNED METHOD FOR VERTICAL RECESS FOR 3D DEVICE INTEGRATION

INDEPENDENT GATE CONTACTS FOR CFET

SEMICONDUCTOR STRUCTURE HAVING STACKED GATES AND METHOD OF MANUFACT...

INVERTED CROSS-COUPLE FOR TOP-TIER FET FOR MULTI-TIER GATE-ON-GATE 3DI

THREE-DIMENSIONAL MEMORY CELL STRUCTURE

INVERTED TOP-TIER FET FOR MULTI-TIER GATE-ON-GATE 3-DIMENSION INTEG...

INTEGRATED HIGH EFFICIENCY GATE ON GATE COOLING

INTEGRATED HIGH EFFICIENCY TRANSISTOR COOLING

POWER-TAP PASS-THROUGH TO CONNECT A BURIED POWER RAIL TO FRONT-SIDE...

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

INTER-TIER POWER DELIVERY NETWORK (PDN) FOR DENSE GATE-ON-GATE 3D L...

MULTI-TIER BACKSIDE POWER DELIVERY NETWORK FOR DENSE GATE-ON-GATE 3...

INTERDIGITATED DEVICE STACK

INTER-LEVEL HANDSHAKE FOR DENSE 3D LOGIC INTEGRATION

DOUBLE CROSS-COUPLE FOR TWO-ROW FLIP-FLOP USING CFET

METHOD OF 3D LOGIC FABRICATION TO SEQUENTIALLY DECREASE PROCESSING...

System and method for hiding refresh cycles in a dynamic type conte...

VARIABLE DETAIL AUTOMATIC INVOCATION OF TRANSISTOR LEVEL TIMING FOR...

Method of partitioning large transistor design to facilitate transi...

Directed least recently used cache replacement method