PERVEZ H. SAGARWALA

Person

GRAND PRAIRIE, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
CMOS integrated circuit device with LDD n-channel transistor and no...
- Patent number 6,759,717
- Issue date Jul 6, 2004
- STMicroelectronics, Inc.
- Pervez Hassan Sagarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM memory cell with increased dielectric integrity
- Patent number 6,518,620
- Issue date Feb 11, 2003
- STMicroelectronics, Inc.
- Tsiu Chiu Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a CMOS integrated circuit device with LDD N-c...
- Patent number 6,221,709
- Issue date Apr 24, 2001
- STMicroelectronics, Inc.
- Pervez Hassan Sagarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shadow memory for a SRAM and method
- Patent number 6,128,243
- Issue date Oct 3, 2000
- STMicroelectronics, Inc.
- Tsiu C. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Shadow memory for a SRAM and method
- Patent number 6,034,886
- Issue date Mar 7, 2000
- STMicroelectronics, Inc.
- Tsiu C. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having selective bias of transistors for low vol...
- Patent number 5,929,695
- Issue date Jul 27, 1999
- STMicroelectronics, Inc.
- Tsiu Chiu Chan
- G05 - CONTROLLING REGULATING
Information Patent Grant
Narrow isolation oxide process
- Patent number 5,895,237
- Issue date Apr 20, 1999
- STMicroelectronics, Inc.
- Tsiu Chiu Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making EEPROM cell structure
- Patent number 5,885,871
- Issue date Mar 23, 1999
- STMicrolelectronics, Inc.
- Tsiu Chiu Chan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
EEPROM MEMORY CELL WITH INCREASED DIELECTRIC INTEGRITY
- Publication number 20010022377
- Publication date Sep 20, 2001
- TSIU CHIU CHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS integrated circuit device with LDD n-channel transistor and no...
- Publication number 20010009796
- Publication date Jul 26, 2001
- Pervez Hassan Sagarwala
- H01 - BASIC ELECTRIC ELEMENTS

PERVEZ H. SAGARWALA

Person

Patents Grantslast 30 patents

CMOS integrated circuit device with LDD n-channel transistor and no...

EEPROM memory cell with increased dielectric integrity

Method of fabricating a CMOS integrated circuit device with LDD N-c...

Shadow memory for a SRAM and method

Shadow memory for a SRAM and method

Integrated circuit having selective bias of transistors for low vol...

Narrow isolation oxide process

Method of making EEPROM cell structure

Patents Applicationslast 30 patents

EEPROM MEMORY CELL WITH INCREASED DIELECTRIC INTEGRITY

CMOS integrated circuit device with LDD n-channel transistor and no...