Peter Beer

Person

Fontainbleau, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for checking output signals of an integrated c...
- Patent number 7,380,182
- Issue date May 27, 2008
- Infineon Technologies AG
- Peter Beer
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory having a test circuit for functional testing of t...
- Patent number 7,302,622
- Issue date Nov 27, 2007
- Infineon Technologies, AG
- Peter Beer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module, test system and method for testing one or a pluralit...
- Patent number 7,231,562
- Issue date Jun 12, 2007
- Infineon Technologies AG
- Carsten Ohlhoff
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for reading out defect information items from...
- Patent number 7,038,956
- Issue date May 2, 2006
- Infineon Technologies AG
- Peter Beer
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic memory cell
- Patent number 7,009,869
- Issue date Mar 7, 2006
- Infineon Technologies AG
- Peter Beer
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory circuit having a redundancy circuit and a method...
- Patent number 6,985,390
- Issue date Jan 10, 2006
- Infineon Technologies AG
- Peter Beer
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and test circuit for testing a dynamic memory circuit
- Patent number 6,862,234
- Issue date Mar 1, 2005
- Infineon Technologies AG
- Martin Versen
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for checking output signals of an integrated c...
- Publication number 20050114734
- Publication date May 26, 2005
- Peter Beer
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory having a test circuit for functional testing of t...
- Publication number 20050041497
- Publication date Feb 24, 2005
- Peter Beer
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and method for reading out defect information items from...
- Publication number 20050030822
- Publication date Feb 10, 2005
- Peter Beer
- G01 - MEASURING TESTING
Information Patent Application
Memory module, test system and method for testing one or a pluralit...
- Publication number 20040260987
- Publication date Dec 23, 2004
- Carsten Ohlhoff
- G11 - INFORMATION STORAGE
Information Patent Application
Method and test circuit for testing a dynamic memory circuit
- Publication number 20040257893
- Publication date Dec 23, 2004
- Martin Versen
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory circuit having a redundancy circuit and a method...
- Publication number 20040246792
- Publication date Dec 9, 2004
- Peter Beer
- G11 - INFORMATION STORAGE
Information Patent Application
Method for writing to a defect address memory, and test circuit hav...
- Publication number 20040153947
- Publication date Aug 5, 2004
- Peter Beer
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamic memory cell
- Publication number 20040151020
- Publication date Aug 5, 2004
- Peter Beer
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Method and apparatus for checking output signals of an integrated c...

Integrated memory having a test circuit for functional testing of t...

Memory module, test system and method for testing one or a pluralit...

Apparatus and method for reading out defect information items from...

Dynamic memory cell

Integrated memory circuit having a redundancy circuit and a method...

Method and test circuit for testing a dynamic memory circuit

Patents Applicationslast 30 patents

Method and apparatus for checking output signals of an integrated c...

Integrated memory having a test circuit for functional testing of t...

Apparatus and method for reading out defect information items from...

Memory module, test system and method for testing one or a pluralit...

Method and test circuit for testing a dynamic memory circuit

Integrated memory circuit having a redundancy circuit and a method...

Method for writing to a defect address memory, and test circuit hav...

Dynamic memory cell