Peter Gregorius

Person

Deutschland, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-port DRAM architecture for accessing different memory partitions
- Patent number 8,914,589
- Issue date Dec 16, 2014
- Infineon Technologies AG
- Peter Gregorius
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system including plural memory controllers and a memory...
- Patent number 8,495,310
- Issue date Jul 23, 2013
- Qimonda AG
- Peter Gregorius
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Interface voltage adjustment based on error detection
- Patent number 8,392,779
- Issue date Mar 5, 2013
- Qimonda AG
- Andreas Schneider
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory with memory cell portions having different acc...
- Patent number 8,305,834
- Issue date Nov 6, 2012
- Qimonda AG
- Michael Richter
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system with extended memory density capability
- Patent number 8,271,827
- Issue date Sep 18, 2012
- Qimonda
- Christoph Bilger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed command and address bus architecture for a memory modul...
- Patent number 8,161,219
- Issue date Apr 17, 2012
- Qimonda AG
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for determining a skew
- Patent number 8,144,755
- Issue date Mar 27, 2012
- Michael Bruennert
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and device for transmitting outgoing useful signals and an o...
- Patent number 8,125,812
- Issue date Feb 28, 2012
- Qimonda AG
- Martin Streibl
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-die memory, apparatus and multi-die memory stack
- Patent number 8,120,958
- Issue date Feb 21, 2012
- Qimonda AG
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory chip and memory system
- Patent number 8,108,643
- Issue date Jan 31, 2012
- Qimonda AG
- Paul Wallner
- G11 - INFORMATION STORAGE
Information Patent Grant
Bus termination system and method
- Patent number 8,041,865
- Issue date Oct 18, 2011
- Qimonda AG
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and memory system comprising a memory device and a me...
- Patent number 8,031,539
- Issue date Oct 4, 2011
- Qimonda AG
- Peter Gregorius
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit
- Patent number 8,015,438
- Issue date Sep 6, 2011
- Qimonda AG
- Michael Bruennert
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with wireless connection
- Patent number 7,928,525
- Issue date Apr 19, 2011
- Qimonda AG
- Christoph Bilger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for storage device with a logic unit and metho...
- Patent number 7,920,433
- Issue date Apr 5, 2011
- Qimonda AG
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Grant
Training connections in a memory arrangement
- Patent number 7,908,232
- Issue date Mar 15, 2011
- Qimonda AG
- Peter Gregorius
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data receiver with clock recovery circuit
- Patent number 7,864,907
- Issue date Jan 4, 2011
- Qimonda AG
- Martin Streibl
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed memory architecture
- Patent number 7,848,153
- Issue date Dec 7, 2010
- Qimonda AG
- Michael Bruennert
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for avoiding steady-state oscillations in the...
- Patent number 7,817,766
- Issue date Oct 19, 2010
- Qimonda AG
- Peter Gregorius
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Horizontal dual in-line memory modules
- Patent number 7,771,206
- Issue date Aug 10, 2010
- Qimonda AG
- Michael Bruennert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory arrangement having efficient arrangement of devices
- Patent number 7,725,647
- Issue date May 25, 2010
- Qimonda AG
- Paul Wallner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase locked loop having reduced inherent noise
- Patent number 7,693,247
- Issue date Apr 6, 2010
- Infineon Technologies AG
- Peter Gregorius
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory device, memory system and method of operating such
- Patent number 7,663,964
- Issue date Feb 16, 2010
- Qimonda AG
- Paul Wallner
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit with selectable data paths
- Patent number 7,646,320
- Issue date Jan 12, 2010
- Qimonda AG
- Johannes Reichart
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method of operating such
- Patent number 7,633,814
- Issue date Dec 15, 2009
- Qimonda AG
- Paul Wallner
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of transferring signals between a memory device and a memory...
- Patent number 7,587,655
- Issue date Sep 8, 2009
- Infineon Technologies AG
- Paul Wallner
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for estimating channel properties of a transmissi...
- Patent number 7,561,639
- Issue date Jul 14, 2009
- Infineon Technologies AG
- Peter Gregorius
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Semiconductor memory system and semiconductor memory chip
- Patent number 7,523,250
- Issue date Apr 21, 2009
- Qimonda AG
- Paul Wallner
- G11 - INFORMATION STORAGE
Information Patent Grant
Data conversion
- Patent number 7,515,075
- Issue date Apr 7, 2009
- Qimonda AG
- Paul Wallner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device for the production of standard-compliant signals
- Patent number 7,474,876
- Issue date Jan 6, 2009
- Infineon Technologies AG
- Jörg Bonhaus
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR MEMORY WITH MEMORY CELL PORTIONS HAVING DIFFERENT ACC...
- Publication number 20110205828
- Publication date Aug 25, 2011
- QIMONDA AG
- Michael Richter
- G11 - INFORMATION STORAGE
Information Patent Application
Stacking Technique for Circuit Devices
- Publication number 20110034045
- Publication date Feb 10, 2011
- QIMONDA AG
- Christoph Bilger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE AND MEMORY SYSTEM COMPRISING A MEMORY DEVICE AND A ME...
- Publication number 20100091588
- Publication date Apr 15, 2010
- Peter Gregorius
- G11 - INFORMATION STORAGE
Information Patent Application
Distributed Command and Address Bus Architecture
- Publication number 20100082871
- Publication date Apr 1, 2010
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PORT DRAM ARCHITECTURE
- Publication number 20100077139
- Publication date Mar 25, 2010
- PETER GREGORIUS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI MASTER DRAM ARCHITECTURE
- Publication number 20100077157
- Publication date Mar 25, 2010
- PETER GREGORIUS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Horizontal Dual In-line Memory Modules
- Publication number 20100062621
- Publication date Mar 11, 2010
- MICHAEL BRUENNERT
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
High Speed Memory Architecture
- Publication number 20100046266
- Publication date Feb 25, 2010
- Michael Bruennert
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked Memory Module
- Publication number 20100032820
- Publication date Feb 11, 2010
- Michael Bruennert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bus Termination System and Method
- Publication number 20100030934
- Publication date Feb 4, 2010
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CONTROLLING A MEMORY MODULE AND MEMORY CONTROL UNIT
- Publication number 20090287957
- Publication date Nov 19, 2009
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit with Improved Data Rate
- Publication number 20090267678
- Publication date Oct 29, 2009
- QIMONDA AG
- Christoph Bilger
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Integrated circuit with wireless connection
- Publication number 20090267084
- Publication date Oct 29, 2009
- QIMONDA AG
- Christoph Bilger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERFACE VOLTAGE ADJUSTMENT BASED ON ERROR DETECTION
- Publication number 20090271678
- Publication date Oct 29, 2009
- Andreas Schneider
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM with Page Access
- Publication number 20090190432
- Publication date Jul 30, 2009
- Christoph BILGER
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHO...
- Publication number 20090175100
- Publication date Jul 9, 2009
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE, METHOD FOR ACCESSING A MEMORY DEVICE AND METHOD FOR...
- Publication number 20090175115
- Publication date Jul 9, 2009
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-die Memory, Apparatus and Multi-die Memory Stack
- Publication number 20090161401
- Publication date Jun 25, 2009
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Application
Memory System With Extended Memory Density Capability
- Publication number 20090150710
- Publication date Jun 11, 2009
- Christoph Bilger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Circuit
- Publication number 20090144583
- Publication date Jun 4, 2009
- Qimonda AG
- Michael Bruennert
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Determining a Skew
- Publication number 20090141843
- Publication date Jun 4, 2009
- Qimonda AG
- Michael Bruennert
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR MONITORING A MEMORY DEVICE
- Publication number 20090129189
- Publication date May 21, 2009
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Application
DATA CONVERSION
- Publication number 20090073010
- Publication date Mar 19, 2009
- QIMONDA AG
- Paul Wallner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND DEVICE FOR TRANSMITTING OUTGOING USEFUL SIGNALS AND AN O...
- Publication number 20080240290
- Publication date Oct 2, 2008
- QIMONDA AG
- Martin Streibl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method For Processing Data in a Memory Arrangement, Memory Arrangem...
- Publication number 20080229033
- Publication date Sep 18, 2008
- Qimonda AG
- Paul Wallner
- G11 - INFORMATION STORAGE
Information Patent Application
Controller
- Publication number 20080222443
- Publication date Sep 11, 2008
- QIMONDA AG
- Paul Wallner
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TRAINING CONNECTIONS IN A MEMORY ARRANGEMENT
- Publication number 20080052256
- Publication date Feb 28, 2008
- Peter Gregorius
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF OPERATING SUCH
- Publication number 20070280007
- Publication date Dec 6, 2007
- Paul Wallner
- G11 - INFORMATION STORAGE
Information Patent Application
DATA RECEIVER WITH CLOCK RECOVERY CIRCUIT
- Publication number 20070258552
- Publication date Nov 8, 2007
- Martin Streibl
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MEMORY DEVICE AND METHOD OF OPERATING SUCH
- Publication number 20070247929
- Publication date Oct 25, 2007
- Paul Wallner
- G11 - INFORMATION STORAGE

Peter Gregorius

Person

Patents Grantslast 30 patents

Multi-port DRAM architecture for accessing different memory partitions

Method and system including plural memory controllers and a memory...

Interface voltage adjustment based on error detection

Semiconductor memory with memory cell portions having different acc...

Memory system with extended memory density capability

Distributed command and address bus architecture for a memory modul...

Method and apparatus for determining a skew

Method and device for transmitting outgoing useful signals and an o...

Multi-die memory, apparatus and multi-die memory stack

Semiconductor memory chip and memory system

Bus termination system and method

Memory device and memory system comprising a memory device and a me...

Memory circuit

Integrated circuit with wireless connection

Method and apparatus for storage device with a logic unit and metho...

Training connections in a memory arrangement

Data receiver with clock recovery circuit

High speed memory architecture

Apparatus and method for avoiding steady-state oscillations in the...

Horizontal dual in-line memory modules

Memory arrangement having efficient arrangement of devices

Phase locked loop having reduced inherent noise

Memory device, memory system and method of operating such

Circuit with selectable data paths

Memory device and method of operating such

Method of transferring signals between a memory device and a memory...

Method and device for estimating channel properties of a transmissi...

Semiconductor memory system and semiconductor memory chip

Data conversion

Device for the production of standard-compliant signals

Patents Applicationslast 30 patents

SEMICONDUCTOR MEMORY WITH MEMORY CELL PORTIONS HAVING DIFFERENT ACC...

Stacking Technique for Circuit Devices

MEMORY DEVICE AND MEMORY SYSTEM COMPRISING A MEMORY DEVICE AND A ME...

Distributed Command and Address Bus Architecture

MULTI-PORT DRAM ARCHITECTURE

MULTI MASTER DRAM ARCHITECTURE

Horizontal Dual In-line Memory Modules

High Speed Memory Architecture

Stacked Memory Module

Bus Termination System and Method

METHOD FOR CONTROLLING A MEMORY MODULE AND MEMORY CONTROL UNIT

Integrated Circuit with Improved Data Rate

Integrated circuit with wireless connection

INTERFACE VOLTAGE ADJUSTMENT BASED ON ERROR DETECTION

DRAM with Page Access

METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHO...

MEMORY DEVICE, METHOD FOR ACCESSING A MEMORY DEVICE AND METHOD FOR...

Multi-die Memory, Apparatus and Multi-die Memory Stack

Memory System With Extended Memory Density Capability

Memory Circuit

Method and Apparatus for Determining a Skew

METHOD AND APPARATUS FOR MONITORING A MEMORY DEVICE

DATA CONVERSION

METHOD AND DEVICE FOR TRANSMITTING OUTGOING USEFUL SIGNALS AND AN O...

Method For Processing Data in a Memory Arrangement, Memory Arrangem...

Controller

TRAINING CONNECTIONS IN A MEMORY ARRANGEMENT

MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF OPERATING SUCH

DATA RECEIVER WITH CLOCK RECOVERY CIRCUIT

MEMORY DEVICE AND METHOD OF OPERATING SUCH