Peter Lee

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Simulation method for transistor unsuitable for existing model
- Patent number 8,285,524
- Issue date Oct 9, 2012
- Elpida Memory, Inc.
- Yasuhiro Namba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation method and simulation program
- Patent number 7,721,234
- Issue date May 18, 2010
- Renesas Technology Corp.
- Peter Maurice Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Output buffer circuit with control circuit for modifying supply vol...
- Patent number 7,123,049
- Issue date Oct 17, 2006
- Renesas Technology Corporation
- Takashi Satou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Output buffer circuit with control circuit for modifying supply vol...
- Patent number 6,952,112
- Issue date Oct 4, 2005
- Renesas Technology Corporation
- Takashi Satou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Output buffer circuit with control circuit for modifying supply vol...
- Patent number 6,937,059
- Issue date Aug 30, 2005
- Renesas Technology Corp.
- Takashi Satou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer-readable storage media stored with a delay library for des...
- Patent number 6,634,015
- Issue date Oct 14, 2003
- Hitachi, Ltd.
- Peter Maurice Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wiringless logical operation circuits
- Patent number 5,742,071
- Issue date Apr 21, 1998
- Hitachi, Ltd.
- Shiroo Kamohara
- B82 - NANO-TECHNOLOGY

Patents Applicationslast 30 patents

Information Patent Application
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
- Publication number 20120064645
- Publication date Mar 15, 2012
- ELPIDA MEMORY, INC.
- Peter LEE
- G01 - MEASURING TESTING
Information Patent Application
SIMULATION METHOD AND SIMULATION PROGRAM
- Publication number 20100199239
- Publication date Aug 5, 2010
- RENESAS TECHNOLOGY CORP.
- Peter Maurice LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATION METHOD FOR TRANSISTOR UNSUITABLE FOR EXISTING MODEL
- Publication number 20100114543
- Publication date May 6, 2010
- ELPIDA MEMORY, INC.
- Yasuhiro NAMBA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Simulation method
- Publication number 20070219770
- Publication date Sep 20, 2007
- Peter Maurice Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATION METHOD AND SIMULATION PROGRAM
- Publication number 20070186194
- Publication date Aug 9, 2007
- Peter Maurice Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Output buffer circuit with control circuit for modifying supply vol...
- Publication number 20050258860
- Publication date Nov 24, 2005
- RENESAS TECHNOLOGY CORP.
- Takashi Satou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit and data processing system
- Publication number 20040070420
- Publication date Apr 15, 2004
- Hitachi, Ltd.
- Takashi Satou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit and data processing system
- Publication number 20040027153
- Publication date Feb 12, 2004
- Takashi Satou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Storage media being readable by a computer, and a method for design...
- Publication number 20010032329
- Publication date Oct 18, 2001
- Hitachi, Ltd.
- Peter Maurice Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Storage media being readable by a computer, and a method for design...
- Publication number 20010029600
- Publication date Oct 11, 2001
- Hitachi, Ltd.
- Peter Maurice Lee
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Simulation method for transistor unsuitable for existing model

Simulation method and simulation program

Output buffer circuit with control circuit for modifying supply vol...

Output buffer circuit with control circuit for modifying supply vol...

Output buffer circuit with control circuit for modifying supply vol...

Computer-readable storage media stored with a delay library for des...

Wiringless logical operation circuits

Patents Applicationslast 30 patents

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

SIMULATION METHOD AND SIMULATION PROGRAM

SIMULATION METHOD FOR TRANSISTOR UNSUITABLE FOR EXISTING MODEL

Simulation method

SIMULATION METHOD AND SIMULATION PROGRAM

Output buffer circuit with control circuit for modifying supply vol...

Semiconductor integrated circuit and data processing system

Semiconductor integrated circuit and data processing system

Storage media being readable by a computer, and a method for design...

Storage media being readable by a computer, and a method for design...