Peter Z. Onufryk

Person

Flanders, NJ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processed wafer of scalable electrical circuits, method for making...
- Patent number 10,410,975
- Issue date Sep 10, 2019
- Microsemi Solutions (U.S.), Inc.
- Bruce Scatchard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for layer-specific LDPC decoding
- Patent number 10,230,396
- Issue date Mar 12, 2019
- Microsemi Solutions (US), Inc.
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layer specific LDPC decoder
- Patent number 9,813,080
- Issue date Nov 7, 2017
- Microsemi Solutions (U.S.), Inc.
- Rino Micheloni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for higher quality log likelihood ratios in LDPC...
- Patent number 9,590,656
- Issue date Mar 7, 2017
- Microsemi Storage Solutions (U.S.), Inc.
- Rino Micheloni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for accumulating soft information in LDPC decoding
- Patent number 9,454,414
- Issue date Sep 27, 2016
- Microsemi Storage Solutions (U.S.), Inc.
- Rino Micheloni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory controller and integrated circuit device for correcting erro...
- Patent number 9,448,881
- Issue date Sep 20, 2016
- Microsemi Storage Solutions (U.S.), Inc.
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for lifetime specific LDPC decoding
- Patent number 9,397,701
- Issue date Jul 19, 2016
- Microsemi Storage Solutions (U.S.), Inc.
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method with reference voltage partitioning for low densi...
- Patent number 9,235,467
- Issue date Jan 12, 2016
- PMC-Sierra US, Inc.
- Rino Micheloni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for mapped I/O routing in an interconnect switch
- Patent number 9,146,890
- Issue date Sep 29, 2015
- PMC-Sierra US, Inc.
- David Alan Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for adjusting a correctable raw bit error rate...
- Patent number 9,128,858
- Issue date Sep 8, 2015
- PMC-Sierra US, Inc.
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method based on LDPC codes for adjusting a correctabl...
- Patent number 9,092,353
- Issue date Jul 28, 2015
- PMC-Sierra US, Inc.
- Rino Micheloni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flexible routing engine for a PCI express switch and method of use
- Patent number 9,025,495
- Issue date May 5, 2015
- David Alan Brown
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for translated routing in an interconnect switch
- Patent number 8,995,302
- Issue date Mar 31, 2015
- PMC-Sierra US, Inc.
- David Alan Brown
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Layer specific attenuation factor LDPC decoder
- Patent number 8,990,661
- Issue date Mar 24, 2015
- PMC-Sierra US, Inc.
- Rino Micheloni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Nonvolatile memory controller with two-stage error correction techn...
- Patent number 8,707,122
- Issue date Apr 22, 2014
- PMC-Sierra US, Inc.
- Rino Micheloni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Shuffler error correction code system and method
- Patent number 8,694,849
- Issue date Apr 8, 2014
- PMC-Sierra US, Inc.
- Rino Micheloni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for routing a data message through a message network
- Patent number 8,656,071
- Issue date Feb 18, 2014
- PMC-Sierra US, Inc.
- Peter Z. Onufryk
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Nonvolatile memory controller with concatenated error correction codes
- Patent number 8,656,257
- Issue date Feb 18, 2014
- PMC-Sierra US, Inc.
- Rino Micheloni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Nonvolatile memory controller with error detection for concatenated...
- Patent number 8,621,318
- Issue date Dec 31, 2013
- PMC-Sierra US, Inc.
- Rino Micheloni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for generating parity data in a nonvolatile memor...
- Patent number 8,601,346
- Issue date Dec 3, 2013
- PMC-Sierra US, Inc.
- Peter Z. Onufryk
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Nonvolatile memory controller with host controller interface for re...
- Patent number 8,588,228
- Issue date Nov 19, 2013
- PMC-Sierra US, Inc.
- Peter Z. Onufryk
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Interrupt technique for a nonvolatile memory controller
- Patent number 8,554,968
- Issue date Oct 8, 2013
- PMC-Sierra, Inc.
- Peter Z. Onufryk
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
PCI express switch and method for multi-port non-transparent switching
- Patent number 8,429,325
- Issue date Apr 23, 2013
- Integrated Device Technology Inc.
- Peter Z. Onufryk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
BCH data correction system and method
- Patent number 8,397,144
- Issue date Mar 12, 2013
- Integrated Device Technology, Inc.
- Christopher I. W. Norrie
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Packet telephony appliance
- Patent number 8,170,007
- Issue date May 1, 2012
- AT&T Intellectual Property II, L.P.
- Mike Chan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for telephony and high-speed data access on a bro...
- Patent number 8,107,479
- Issue date Jan 31, 2012
- AT&T Intellectual Property II, L.P.
- Steven Michael Bellovin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Integrated memory for storing egressing packet data, replay data an...
- Patent number 7,852,867
- Issue date Dec 14, 2010
- Integrated Deoice Technology, Inc.
- Siukwin Tsang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Scheduler for a multiprocessing computing system
- Patent number 7,827,555
- Issue date Nov 2, 2010
- Integrated Device Technology, Inc.
- Mitrajit Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated memory for storing egressing packet data, replay data an...
- Patent number 7,773,591
- Issue date Aug 10, 2010
- Integrated Device Technology, Inc.
- Siukwin Tsang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method of scheduling computing threads
- Patent number 7,634,774
- Issue date Dec 15, 2009
- Integrated Device Technology, Inc.
- Peter Zenon Onufryk
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE
- Publication number 20240329129
- Publication date Oct 3, 2024
- Intel Corporation
- Sridhar Muthrasanallur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...
- Publication number 20240311330
- Publication date Sep 19, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC SWITCHING OF DATA TRANSFERS BETWEEN SIDEBAND AND MAINBAND
- Publication number 20240111701
- Publication date Apr 4, 2024
- Intel Corporation
- Aruni P. Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTE...
- Publication number 20240030172
- Publication date Jan 25, 2024
- Intel Corporation
- Debendra Das Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR HIGHER QUALITY LOG LIKELIHOOD RATIOS IN LDPC...
- Publication number 20140281800
- Publication date Sep 18, 2014
- PMC-SIERRA US, INC.
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD WITH REFERENCE VOLTAGE PARTITIONING FOR LOW DENSI...
- Publication number 20140281823
- Publication date Sep 18, 2014
- PMC-SIERRA US, INC.
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ACCUMULATING SOFT INFORMATION IN LDPC DECODING
- Publication number 20140281828
- Publication date Sep 18, 2014
- PMC-SIERRA US, INC.
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET TELEPHONY APPLIANCE
- Publication number 20090052439
- Publication date Feb 26, 2009
- Mike Chan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Integrated Memory for Storing Egressing Packet Data, Replay Data an...
- Publication number 20090010252
- Publication date Jan 8, 2009
- Integrated Device Technology, Inc.
- Siukwin Tsang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Integrated Memory for Storing Egressing Packet Data, Replay Data an...
- Publication number 20090010279
- Publication date Jan 8, 2009
- Siukwin Tsang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Expansion of cross-domain addressing for PCI-express packets passin...
- Publication number 20060282603
- Publication date Dec 14, 2006
- Integrated Device Technology, Inc.
- Peter Z. Onufryk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementation of load linked and store conditional operations
- Publication number 20060161919
- Publication date Jul 20, 2006
- Peter Z. Onufryk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduler for a multiprocessing computing system
- Publication number 20060059487
- Publication date Mar 16, 2006
- Integrated Device Technology, Inc.
- Mitrajit Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method of scheduling computing threads
- Publication number 20060059485
- Publication date Mar 16, 2006
- Peter Zenon Onufryk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for telephony and high-speed data access on a bro...
- Publication number 20050041797
- Publication date Feb 24, 2005
- Steven Michael Bellovin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Peter Z. Onufryk

Person

Patents Grantslast 30 patents

Processed wafer of scalable electrical circuits, method for making...

Method and apparatus for layer-specific LDPC decoding

Layer specific LDPC decoder

System and method for higher quality log likelihood ratios in LDPC...

System and method for accumulating soft information in LDPC decoding

Memory controller and integrated circuit device for correcting erro...

System and method for lifetime specific LDPC decoding

System and method with reference voltage partitioning for low densi...

Method and apparatus for mapped I/O routing in an interconnect switch

Apparatus and method for adjusting a correctable raw bit error rate...

Apparatus and method based on LDPC codes for adjusting a correctabl...

Flexible routing engine for a PCI express switch and method of use

Method and apparatus for translated routing in an interconnect switch

Layer specific attenuation factor LDPC decoder

Nonvolatile memory controller with two-stage error correction techn...

Shuffler error correction code system and method

System and method for routing a data message through a message network

Nonvolatile memory controller with concatenated error correction codes

Nonvolatile memory controller with error detection for concatenated...

System and method for generating parity data in a nonvolatile memor...

Nonvolatile memory controller with host controller interface for re...

Interrupt technique for a nonvolatile memory controller

PCI express switch and method for multi-port non-transparent switching

BCH data correction system and method

Packet telephony appliance

Method and system for telephony and high-speed data access on a bro...

Integrated memory for storing egressing packet data, replay data an...

Scheduler for a multiprocessing computing system

Integrated memory for storing egressing packet data, replay data an...

System and method of scheduling computing threads

Patents Applicationslast 30 patents

TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE

ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...

DYNAMIC SWITCHING OF DATA TRANSFERS BETWEEN SIDEBAND AND MAINBAND

THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTE...

SYSTEM AND METHOD FOR HIGHER QUALITY LOG LIKELIHOOD RATIOS IN LDPC...

SYSTEM AND METHOD WITH REFERENCE VOLTAGE PARTITIONING FOR LOW DENSI...

SYSTEM AND METHOD FOR ACCUMULATING SOFT INFORMATION IN LDPC DECODING

PACKET TELEPHONY APPLIANCE

Integrated Memory for Storing Egressing Packet Data, Replay Data an...

Integrated Memory for Storing Egressing Packet Data, Replay Data an...

Expansion of cross-domain addressing for PCI-express packets passin...

Implementation of load linked and store conditional operations

Scheduler for a multiprocessing computing system

System and method of scheduling computing threads

Method and system for telephony and high-speed data access on a bro...