Philip A. Ferolito

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reducing latency in serializer-deserializer links
- Patent number 8,832,336
- Issue date Sep 9, 2014
- MoSys, Inc.
- Michael J. Morrison
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming of DIMM termination resistance values
- Patent number 8,710,862
- Issue date Apr 29, 2014
- Google Inc.
- Philip Arnold Ferolito
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Optimal channel design for memory devices for providing a high-spee...
- Patent number 8,675,429
- Issue date Mar 18, 2014
- Google Inc.
- Min Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing latency in serializer-deserializer links
- Patent number 8,527,676
- Issue date Sep 3, 2013
- MoSys, Inc.
- Michael J. Morrison
- G11 - INFORMATION STORAGE
Information Patent Grant
Communication interface and protocol
- Patent number 8,370,725
- Issue date Feb 5, 2013
- MoSys, Inc.
- Michael J. Miller
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optimal channel design for memory devices for providing a high-spee...
- Patent number 8,279,690
- Issue date Oct 2, 2012
- Google Inc.
- Min Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programming of DIMM termination resistance values
- Patent number 8,169,233
- Issue date May 1, 2012
- Google Inc.
- Philip Arnold Ferolito
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Optimal channel design for memory devices for providing a high-spee...
- Patent number 8,111,566
- Issue date Feb 7, 2012
- Google, Inc.
- Min Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing additional space between an integrated circuit and a circ...
- Patent number 8,080,874
- Issue date Dec 20, 2011
- Google Inc.
- Jeremy Werner
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Testing and error recovery across multiple switching fabrics
- Patent number 7,876,693
- Issue date Jan 25, 2011
- Alcatel-Lucent USA Inc.
- Gregory S. Mathews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multicast packet queuing
- Patent number 7,609,693
- Issue date Oct 27, 2009
- Alcatel-Lucent USA Inc.
- Eric Anderson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flow control in a distributed scalable, shared memory switching fab...
- Patent number 7,525,917
- Issue date Apr 28, 2009
- Acatel-Lucent USA Inc.
- Philip Ferolito
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Using reassembly queue sets for packet reassembly
- Patent number 7,394,822
- Issue date Jul 1, 2008
- Lucent Technologies Inc.
- Gregory S. Mathews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Distributed weighted fair arbitration and forwarding
- Patent number 7,283,558
- Issue date Oct 16, 2007
- Lucent Technologies Inc.
- Philip Ferolito
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optimal load balancing across multiple switching fabrics
- Patent number 7,242,691
- Issue date Jul 10, 2007
- Lucent Technologies Inc.
- Gregory S. Mathews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed chip-to-chip communication interface
- Patent number 7,180,949
- Issue date Feb 20, 2007
- Lucent Technologies Inc.
- Bendik Kleveland
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed chip-to-chip communication interface with signal trace r...
- Patent number 7,134,056
- Issue date Nov 7, 2006
- Lucent Technologies Inc.
- Bendik Kleveland
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for fair and efficient scheduling of variable-...
- Patent number 6,044,061
- Issue date Mar 28, 2000
- Cabletron Systems, Inc.
- Gunes Aybay
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for identifying ports and forwarding packets in a...
- Patent number 5,999,531
- Issue date Dec 7, 1999
- Cabletron Systems, Inc.
- Philip Arnold Ferolito
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Auxiliary register file accessing technique
- Patent number 5,845,307
- Issue date Dec 1, 1998
- Sun Microsystems, Inc.
- J. Arjun Prabhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flip-flop with full scan capability
- Patent number 5,668,490
- Issue date Sep 16, 1997
- Sun Microsystems, Inc.
- Sundari S. Mitra
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock switching apparatus and method for computer systems
- Patent number 5,274,678
- Issue date Dec 28, 1993
- Intel Corporation
- Philip A. Ferolito
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Reducing Latency In Serializer-Deserializer Links
- Publication number 20120221882
- Publication date Aug 30, 2012
- MoSys, Inc.
- Michael J. Morrison
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROGRAMMING OF DIMM TERMINATION RESISTANCE VALUES
- Publication number 20120206165
- Publication date Aug 16, 2012
- Google Inc.
- Philip Arnold Ferolito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATION INTERFACE AND PROTOCOL
- Publication number 20110191647
- Publication date Aug 4, 2011
- Michael J. Miller
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Reducing Latency in Serializer-Deserializer Links
- Publication number 20110191619
- Publication date Aug 4, 2011
- MoSys Inc.
- Michael J. Morrison
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROGRAMMING OF DIMM TERMINATION RESISTANCE VALUES
- Publication number 20110095783
- Publication date Apr 28, 2011
- Google Inc.
- Philip Arnold Ferolito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Testing and error recovery across multiple switching fabrics
- Publication number 20040037277
- Publication date Feb 26, 2004
- Gregory S. Mathews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multicast packet queuing
- Publication number 20040017810
- Publication date Jan 29, 2004
- Eric Anderson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
High-speed chip-to-chip communication interface with signal trace r...
- Publication number 20040003163
- Publication date Jan 1, 2004
- Bendik Kleveland
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
High-speed chip-to-chip communication interface
- Publication number 20030236939
- Publication date Dec 25, 2003
- Bendik Kleveland
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Using reassembly queue sets for packet reassembly
- Publication number 20030223458
- Publication date Dec 4, 2003
- Gregory S. Mathews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Flow control in a distributed scalable, shared memory switching fab...
- Publication number 20030223448
- Publication date Dec 4, 2003
- Philip Ferolito
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Optimal load balancing across multiple switching fabrics
- Publication number 20030223438
- Publication date Dec 4, 2003
- Gregory S. Mathews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Distributed weighted fair arbitration and forwarding
- Publication number 20030223420
- Publication date Dec 4, 2003
- Philip Ferolito
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Philip A. Ferolito

Person

Patents Grantslast 30 patents

Reducing latency in serializer-deserializer links

Programming of DIMM termination resistance values

Optimal channel design for memory devices for providing a high-spee...

Reducing latency in serializer-deserializer links

Communication interface and protocol

Optimal channel design for memory devices for providing a high-spee...

Programming of DIMM termination resistance values

Optimal channel design for memory devices for providing a high-spee...

Providing additional space between an integrated circuit and a circ...

Testing and error recovery across multiple switching fabrics

Multicast packet queuing

Flow control in a distributed scalable, shared memory switching fab...

Using reassembly queue sets for packet reassembly

Distributed weighted fair arbitration and forwarding

Optimal load balancing across multiple switching fabrics

High-speed chip-to-chip communication interface

High-speed chip-to-chip communication interface with signal trace r...

Method and apparatus for fair and efficient scheduling of variable-...

Method and system for identifying ports and forwarding packets in a...

Auxiliary register file accessing technique

Flip-flop with full scan capability

Clock switching apparatus and method for computer systems

Patents Applicationslast 30 patents

Reducing Latency In Serializer-Deserializer Links

PROGRAMMING OF DIMM TERMINATION RESISTANCE VALUES

COMMUNICATION INTERFACE AND PROTOCOL

Reducing Latency in Serializer-Deserializer Links

PROGRAMMING OF DIMM TERMINATION RESISTANCE VALUES

Testing and error recovery across multiple switching fabrics

Multicast packet queuing

High-speed chip-to-chip communication interface with signal trace r...

High-speed chip-to-chip communication interface

Using reassembly queue sets for packet reassembly

Flow control in a distributed scalable, shared memory switching fab...

Optimal load balancing across multiple switching fabrics

Distributed weighted fair arbitration and forwarding