Philip Damberg

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 11,189,595
- Issue date Nov 30, 2021
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 10,756,049
- Issue date Aug 25, 2020
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 9,761,558
- Issue date Sep 12, 2017
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip assembly and method for making same
- Patent number 9,716,075
- Issue date Jul 25, 2017
- Tessera, Inc.
- Teck-Gyu Kang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Substrate and assembly thereof with dielectric removal for increase...
- Patent number 9,666,450
- Issue date May 30, 2017
- Tessera, Inc.
- Kazuo Sakuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a fan-out WLP with package
- Patent number 9,337,165
- Issue date May 10, 2016
- Tessera, Inc.
- Hiroaki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate and assembly thereof with dielectric removal for increase...
- Patent number 9,318,460
- Issue date Apr 19, 2016
- Tessera, Inc.
- Kazuo Sakuma
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 9,252,122
- Issue date Feb 2, 2016
- Invensas Corporation
- Ellis Chau
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor chip assembly and method for making same
- Patent number 9,137,903
- Issue date Sep 15, 2015
- Tessera, Inc.
- Teck-Gyu Kang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Impedence controlled packages with metal sheet or 2-layer RDL
- Patent number 9,136,197
- Issue date Sep 15, 2015
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 9,105,483
- Issue date Aug 11, 2015
- Invensas Corporation
- Ellis Chau
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 9,041,227
- Issue date May 26, 2015
- Invensas Corporation
- Ellis Chau
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Impedance controlled packages with metal sheet or 2-layer rdl
- Patent number 8,981,579
- Issue date Mar 17, 2015
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assembly comprising dielectric structures with diff...
- Patent number 8,957,520
- Issue date Feb 17, 2015
- Tessera, Inc.
- Hiroaki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of fabricating a flip chip package for dram with two underf...
- Patent number 8,951,845
- Issue date Feb 10, 2015
- Invensas Corporation
- Kazuo Sakuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making wire bond vias and microelectronic package having...
- Patent number 8,940,630
- Issue date Jan 27, 2015
- Invensas Corporation
- Philip Damberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out microelectronic unit WLP having interconnects comprising a...
- Patent number 8,890,304
- Issue date Nov 18, 2014
- Tessera, Inc.
- Hiroaki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate and assembly thereof with dielectric removal for increase...
- Patent number 8,884,432
- Issue date Nov 11, 2014
- Tessera, Inc.
- Kazuo Sakuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 8,836,136
- Issue date Sep 16, 2014
- Invensas Corporation
- Ellis Chau
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Microelectronic assembly with joined bond elements having lowered i...
- Patent number 8,816,514
- Issue date Aug 26, 2014
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High strength through-substrate vias
- Patent number 8,785,790
- Issue date Jul 22, 2014
- Invensas Corporation
- Cyprian Emeka Uzoh
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Impedance controlled packages with metal sheet or 2-layer RDL
- Patent number 8,786,083
- Issue date Jul 22, 2014
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip package for DRAM with two underfill materials
- Patent number 8,637,992
- Issue date Jan 28, 2014
- Invensas Corporation
- Kazuo Sakuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro pin grid array with pin motion isolation
- Patent number 8,531,039
- Issue date Sep 10, 2013
- Tessera, Inc.
- Philip Damberg
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Chip with sintered connections to package
- Patent number 8,525,338
- Issue date Sep 3, 2013
- Tessera, Inc.
- Hiroaki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-thin near-hermetic package based on rainier
- Patent number 8,508,036
- Issue date Aug 13, 2013
- Tessera, Inc.
- Kenneth Allen Honer
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Microelectronic assembly with joined bond elements having lowered i...
- Patent number 8,410,618
- Issue date Apr 2, 2013
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 8,404,520
- Issue date Mar 26, 2013
- Invensas Corporation
- Ellis Chau
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Microelectronic assembly with joined bond elements having lowered i...
- Patent number 8,008,785
- Issue date Aug 30, 2011
- Tessera Research LLC
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip packages and assemblies with chip carrier units
- Patent number 7,732,912
- Issue date Jun 8, 2010
- Tessera, Inc.
- Philip Damberg
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20220165703
- Publication date May 26, 2022
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Package-on-package Assembly With Wire Bond Vias
- Publication number 20210035948
- Publication date Feb 4, 2021
- Invensas Corporation
- Ellis Chau
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20180026007
- Publication date Jan 25, 2018
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor chip assembly and method for making same
- Publication number 20170309593
- Publication date Oct 26, 2017
- Tessera, Inc.
- Teck-Gyu KANG
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Fan-out WLP with package
- Publication number 20160254247
- Publication date Sep 1, 2016
- Tessera, Inc.
- Hiroaki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASE...
- Publication number 20160233109
- Publication date Aug 11, 2016
- Tessera, Inc.
- Kazuo Sakuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP ASSEMBLY AND METHOD FOR MAKING SAME
- Publication number 20160005711
- Publication date Jan 7, 2016
- Tessera, Inc.
- Teck-Gyu Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20150255424
- Publication date Sep 10, 2015
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH STRENGTH THROUGH-SUBSTRATE VIAS
- Publication number 20150146393
- Publication date May 28, 2015
- Invensas Corporation
- CYPRIAN EMEKA UZOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fan-Out WLP With Package
- Publication number 20150044824
- Publication date Feb 12, 2015
- Tessera, Inc.
- Hiroaki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASE...
- Publication number 20150028480
- Publication date Jan 29, 2015
- Tessera, Inc.
- Kazuo Sakuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPEDANCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL
- Publication number 20140291871
- Publication date Oct 2, 2014
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING WIRE BOND VIAS AND MICROELECTRONIC PACKAGE HAVING...
- Publication number 20140220744
- Publication date Aug 7, 2014
- Invensas Corporation
- Philip Damberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS
- Publication number 20140141568
- Publication date May 22, 2014
- Invensas Corporation
- Kazuo Sakuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED I...
- Publication number 20140124565
- Publication date May 8, 2014
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20130328219
- Publication date Dec 12, 2013
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN NEAR-HERMETIC PACKAGE BASED ON RAINIER
- Publication number 20130316501
- Publication date Nov 28, 2013
- Tessera, Inc.
- Kenneth Allen Honer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED I...
- Publication number 20130292834
- Publication date Nov 7, 2013
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20130200533
- Publication date Aug 8, 2013
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS
- Publication number 20130134602
- Publication date May 30, 2013
- Invensas Corporation
- Kazuo Sakuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH STRENGTH THROUGH-SUBSTRATE VIAS
- Publication number 20130118784
- Publication date May 16, 2013
- Invensas Corporation
- Cyprian Uzoh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20130095610
- Publication date Apr 18, 2013
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20130093087
- Publication date Apr 18, 2013
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20130093088
- Publication date Apr 18, 2013
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP PACKAGE ASSEMBLY AND METHOD FOR MAKING SAME
- Publication number 20120313238
- Publication date Dec 13, 2012
- Tessera Research LLC
- Hiroaki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPEDENCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL
- Publication number 20120313228
- Publication date Dec 13, 2012
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASE...
- Publication number 20120313242
- Publication date Dec 13, 2012
- Tessera, Inc.
- Kazuo Sakuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FAN-OUT WLP WITH PACKAGE
- Publication number 20120313253
- Publication date Dec 13, 2012
- Tessera, Inc.
- Yoshikuni Nakadaira
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP WITH SINTERED CONNECTIONS TO PACKAGE
- Publication number 20120313264
- Publication date Dec 13, 2012
- Teresa, Inc.
- Hiroaki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP PACKAGE ASSEMBLY AND METHOD FOR MAKING SAME
- Publication number 20120286416
- Publication date Nov 15, 2012
- Tessera Research LLC
- Hiroaki Sato
- H01 - BASIC ELECTRIC ELEMENTS

Philip Damberg

Person

Patents Grantslast 30 patents

Package-on-package assembly with wire bond vias

Package-on-package assembly with wire bond vias

Package-on-package assembly with wire bond vias

Semiconductor chip assembly and method for making same

Substrate and assembly thereof with dielectric removal for increase...

Method for manufacturing a fan-out WLP with package

Substrate and assembly thereof with dielectric removal for increase...

Package-on-package assembly with wire bond vias

Semiconductor chip assembly and method for making same

Impedence controlled packages with metal sheet or 2-layer RDL

Package-on-package assembly with wire bond vias

Package-on-package assembly with wire bond vias

Impedance controlled packages with metal sheet or 2-layer rdl

Microelectronic assembly comprising dielectric structures with diff...

Methods of fabricating a flip chip package for dram with two underf...

Method of making wire bond vias and microelectronic package having...

Fan-out microelectronic unit WLP having interconnects comprising a...

Substrate and assembly thereof with dielectric removal for increase...

Package-on-package assembly with wire bond vias

Microelectronic assembly with joined bond elements having lowered i...

High strength through-substrate vias

Impedance controlled packages with metal sheet or 2-layer RDL

Flip chip package for DRAM with two underfill materials

Micro pin grid array with pin motion isolation

Chip with sintered connections to package

Ultra-thin near-hermetic package based on rainier

Microelectronic assembly with joined bond elements having lowered i...

Package-on-package assembly with wire bond vias

Microelectronic assembly with joined bond elements having lowered i...

Semiconductor chip packages and assemblies with chip carrier units

Patents Applicationslast 30 patents

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

Package-on-package Assembly With Wire Bond Vias

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

Semiconductor chip assembly and method for making same

Fan-out WLP with package

SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASE...

SEMICONDUCTOR CHIP ASSEMBLY AND METHOD FOR MAKING SAME

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

HIGH STRENGTH THROUGH-SUBSTRATE VIAS

Fan-Out WLP With Package

SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASE...

IMPEDANCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL

METHOD OF MAKING WIRE BOND VIAS AND MICROELECTRONIC PACKAGE HAVING...

FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS

MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED I...

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

ULTRA-THIN NEAR-HERMETIC PACKAGE BASED ON RAINIER

MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED I...

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS

HIGH STRENGTH THROUGH-SUBSTRATE VIAS

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

SEMICONDUCTOR CHIP PACKAGE ASSEMBLY AND METHOD FOR MAKING SAME

IMPEDENCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL

SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASE...

FAN-OUT WLP WITH PACKAGE

CHIP WITH SINTERED CONNECTIONS TO PACKAGE

SEMICONDUCTOR CHIP PACKAGE ASSEMBLY AND METHOD FOR MAKING SAME