Patent Grant
9136197
Microelectronic chips are typically flat bodies with oppositely facing, generally planar front and rear surfaces with edges extending between these surfaces. Chips generally have contacts, sometimes also referred to as pads or bond pads, on the front surface which are electrically connected to the circuits within the chip. Chips are typically packaged by enclosing them with a suitable material to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit (e.g., a circuit in an electronic product such as a computer or a cell phone) by connecting the package terminals to matching lands on a printed circuit board (PCB) by a suitable connection method such as soldering.
Microelectronic packages may be fabricated at the wafer level; that is, the enclosure, terminations and other features that constitute the package, are fabricated while the chips, or die, are still in a wafer form. After the die has been formed, the wafer is subjected to a number of additional process steps to form the package structure on the wafer, and the wafer is then diced to free the individually packaged die. Wafer level processing can be an efficient fabrication method because the footprint of each die package may be made identical, or nearly identical, to the size of the die itself, resulting in very efficient utilization of area on the printed circuit board to which the packaged die is attached.
A common technique for forming electrically conductive connections between a microelectronic chip and one or more other electronic components is through wirebonding. Conventionally, a wirebonding tool attaches the end of a wire to a pad on a microelectronic chip using thermal and/or ultrasonic energy and then loops the wire to a contact on the other electronic component and forms a second bond thereto using thermal and/or ultrasonic forces.
As discussed in U.S. application Ser. No. 12/722,784, filed on Mar. 12, 2010 and U.S. application Ser. No. 12/722,799, filed on Mar. 12, 2010, the disclosures of which are incorporated herein by reference, as well as U.S. application entitled Metal Can Impedance Control Structure, filed by the same assignee herein, on Sep. 16, 2010, the disclosure of which is also incorporated by reference, one of the problems with wire-bond technology inventors have recognized that one of the problems with wirebond technology is that electromagnetic transmissions along a wire can extend into space surrounding the wire, inducing currents in nearby conductors and causing unwanted radiation and detuning of the line. Wirebonds generally are also subject to self-inductances and are subject to external noise (e.g. from nearby electronic components). In the end, this creates electrical impedance problems. These problems can become more serious as the pitch between contacts on microelectronic chips and other electronic components becomes smaller, as the chips operate at higher frequencies, and as the use of multiple raw pads becomes more common.
Various structures and techniques for manufacturing are described herein for a microelectronic assembly. In one embodiment, a microelectronic assembly includes an interconnection element, a microelectronic device, a plurality of raised conductive elements, a surface conductive element, and a bond element. The interconnection element may be a dielectric element that has a plurality of element contacts and at least one reference contact on the surface of the interconnection element. The microelectronic device overlies the dielectric element and has a rear surface overlying the dielectric element, an opposed front surface with device contacts exposed thereat, and at least one surface conductive element attached to the front surface. A plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential.
In one embodiment, substantial portions of each of the conductive elements may be a length that is at least 25% of the total length of each conductive element. Alternatively, the substantial portion of each conductive element may be at least 1 millimeter. Additionally, the first and second edges may meet at a corner of the microelectronic device.
In another embodiment, the bond element may be a first bond element extending beyond a first edge of the microelectronic device. There may also be a second bond element extending beyond a second edge of the microelectronic device and connecting the at least one surface conductive element to a second reference contact of the interconnection element. Alternatively, the bond element may be positioned between at least two of the plurality of raised conductive elements. In yet another alternative, the bond element may extend in a direction transverse to the direction in which at least some of the plurality of raised conductive elements extend.
In another embodiment, at least one of the plurality of raised conductive elements extends beyond a first edge of the microelectronic device and the bond element extends beyond the first edge. The raised conductive elements may include bond wires. Alternatively, all of the conductive elements are bond wires.
In one embodiment, the surface conductive element may be a power plane, a ground plane, or a combination of a power and ground plane. The surface conductive element may also be connectable to a fixed voltage source. Alternatively, the surface conductive element may further reduce an inductance in the electrical connection between the device contact and a source of fixed voltage.
In another embodiment, the surface conductive element may be comprised of multiple sections, wherein at least a first section may be a power plane and a second section may be a ground plane. The first section may be adjacent one edge of the device contacts and the second section may be adjacent the opposed edge of the device contacts. Alternatively, the first and second sections may be adjacent the same edge of the device contacts.
In one embodiment, the first section may be further comprised of a first portion and a second portion, wherein device contacts extend therebetween. In one embodiment, there may be another bond element that electrically connects the first and second portions of the first section. Additionally, the second section may also be further comprised of a first portion and a second portion, and the device contacts may also further extend therebetween. Another bond element may be used to electrically connect the first and second portions of the second section.
In still another embodiment, another bond element may be used to electrically connect device contacts with the first portion or second portion of at least one of the first section and second sections. Alternatively, another bond element may connect at least one device contact with at least one surface conductive element.
Turning now to another aspect of the presently disclosed embodiments, a microelectronic assembly includes an interconnection element having a face, a microelectronic device, a metal plane, and first and second bond elements. The microelectronic device may overly the face of the interconnection element and may have a plurality of first device contacts disposed the surface of the microelectronic device. An at least one second device contact may also be disposed at the surface and at least one trace may be deposited on the surface and electrically connected to the interconnection element. The at least one trace may electrically connect at least one of the first device contacts with the at least one second device contact. At least one first bond element electrically connects the at least one second device contact with at least one of the element contacts. At least one metal plane may be electrically connected to the interconnection element and attached to the microelectronic device at a height from the surface greater than a height of the at least one trace from the surface. The at least one metal plane may be connectable to a source of reference potential, such that a desired impedance may be achieved for the at least one trace. The at least one trace may have at least a substantial portion extending in a direction substantially parallel to a direction in which the metal plane extends. At least one bond element electrically connects the metal plane with a reference element of the interconnection element, which may be electrically connectable with a source of reference potential.
In one embodiment, the substantial portion of the at least one trace may be a length that is at least 25% of the total length of the at least one trace or have a length of at least 1 millimeter.
In one embodiment, the second bond element extends beyond a first edge of the microelectronic device, and the second bond element extends beyond a second edge of the microelectronic device. The first and second edges of the microelectronic device meet at a corner of the microelectronic device.
In one embodiment, the first bond element may be a plurality of first bond elements and the at least one second bond may be positioned between at least two of the plurality of first bond elements. Alternatively, the at least one second bond element extends in a direction transverse to the direction in which the at least one first bond element extends.
In one embodiment, the metal plane reduces an inductance in the electrical connection between the device contact and a source of fixed voltage. Alternatively, the metal plane may be a power plane, a ground plane, or a combination of a ground plane and a power plane. Additionally, the metal plane may be connectable to a fixed voltage source.
In another embodiment, the at least one first bond element or the at least one second bond element includes a bond wire. Alternatively, the at least one first bond element or the at least one second bond element may be a bond wire.
In one embodiment, the metal plane may be comprised of multiple sections, wherein at least one first section may be a power plane and a second section may be a ground plane. The first section may be adjacent one edge of the device contacts and the second section may be adjacent the opposed edge of the device contacts. Alternatively, the first and second sections may be adjacent the same edge of the device contacts. Device contacts may extend between each of the first portions, each of the second portions, or both the first and second sections.
A third bond element may additionally electrically connect the first and second portions of the first section. Alternatively, the third bond element may electrically connect the first and second portions of the second section. Additionally, the third bond element may electrically connect device contacts with the first portion or second portion of either or both the first section and second section. Furthermore, the third bond element may electrically connect device contacts with the first portion or second portion of at least one of the first section and second sections.
In another embodiment, at least one third bond element electrically connects at least one device contact with at least one surface conductive element. In still another embodiment, the at least one third bond element electrically connects the metal plane with a reference contact of the interconnection element.
In one embodiment, the microelectronic assembly includes a first microelectronic device, a second microelectronic device, and the reference conductor may be a first reference conductor. The first and second microelectronic devices have a plurality of third device contacts disposed at a surface remote from the first microelectronic device. At least one fourth device contact may be disposed at the surface, and at least one trace may extend along the surface and electrically connect at least one of the third device contacts with the at least one fourth device contact. The at least one second reference conductor may overlie the surface of the second microelectronic device at a height from the surface greater than a height of the at least one trace from the surface of the second microelectronic device. The at least one second reference conductor may be connectable to a source of reference potential, such that a desired impedance may be achieved for the at least one trace of the second microelectronic device. The second reference conductor has at least a substantial portion extending in a direction substantially parallel to a direction in which the at least one trace of the second microelectronic device extends.
In another aspect of the present invention, a microelectronic assembly includes an interconnection element, a microelectronic device, a conductive plane, a plurality of traces, contacts, and bond elements electrically connecting the components of the assembly. Interconnection element includes a dielectric element, a plurality of element contacts and at least one reference contact thereon. The microelectronic device may have a rear surface overlying the dielectric element and a front surface remote therefrom. Device contacts may be exposed at the front surface. A conductive plane can overlie a portion of the front surface and be insulated from the front surface of the microelectronic device. A plurality of traces overlying a surface of the conductive plane is insulated from the conductive plane. The traces are electrically connected with the element contacts and have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. A first bond element may electrically connect the at least one conductive plane with the at least one reference contact. The at least one reference contact is connectable to a source of reference potential. A plurality of second bond elements may be used to electrically connect device contacts with the traces.
In one embodiment of this aspect, the surface of the conductive plane over which the traces extend is a surface facing away from the front surface of the microelectronic device.
In another embodiment, the substantial portion of each trace has a length that is at least 25% of the total length of each individual respective trace. Alternatively, substantial portions of the traces are lengths of at least 1 millimeter.
In another embodiment, the conductive plane is a power plane. Alternatively, the conductive plane is a ground plane. In yet another alternative embodiment, the conductive plane includes a first conductive plane being a power plane and a second conductive plane being a ground plane.
In another embodiment, the surface of the conductive element is comprised of multiple sections, wherein at least a first section is a power plane and a second section is a ground plane. The first section may be adjacent one edge of the device contacts and the second section may be adjacent the opposed edge of the device contacts. Alternatively, first and second sections are adjacent the same edge of the device contacts.
In another embodiment, the first section is comprised of a first portion and a second portion, and the device contacts extend between the first and second portions. Alternatively, the second section is comprised of a first portion and a second portion, and the device contacts extend between the first and second portions.
In another embodiment, the second section is comprised of a third portion and a fourth portion, and the device contacts extend between the third and fourth portions. The first and second portions of the first conductive plane are ground planes and the third and fourth portions of the second conductive plane are power planes. In such embodiment, the first and third portions provide ground and power connections for off-chip drivers, and the second and fourth portions providing ground and power connections for circuitry other than for the off-chip drivers.
In another embodiment, the conductive plane is connectable to a fixed voltage source.
In another embodiment, at least one third bond element electrically connects the first and second portions of the first section. Alternatively, at least one third bond element electrically connects the first and second portions of the second section.
In still another embodiment, at least one third bond element electrically connects device contacts with the first portion or second portion of at least one of the first section and second sections.
In yet another embodiment, at least one third bond element electrically connects at least one device contact with at least one conductive plane. Alternatively, the at least one third bond element electrically connecting the conductive plane with a reference contact of the interconnection element.
In another embodiment, an insulating layer may be positioned between the conductive plane and the plurality of traces. The insulating layer may be used to insulate the plurality of traces from the conductive plane. Alternatively, conductive vias extending through the insulating layer. The first bond element may be electrically connected to the at least one conductive plane through the conductive vias.
In yet another alternative embodiment, a ground connection may be connected to the conductive vias, and the first bond element may be electrically connected to the at least one conductive plane through the ground connection and conductive vias.
In still another alternative embodiment, there may be a second microelectronic device that has a rear surface and an opposed front surface with device contacts thereon. The rear surface of the second microelectronic device may be adjacent the rear surface of the first microelectronic device. The interconnection element further may further include an opening and the device contacts of the second microelectronic device may be exposed through the opening.
In another aspect of the present invention, the microelectronic assembly includes an interconnection element, a microelectronic device, traces, and bond wires electrically connecting the components of the microelectronic assembly. There is a dielectric element that has a plurality of element contacts and at least one reference contact on its surface. The microelectronic device may have a rear surface that overlies the dielectric element, and a front surface remote therefrom. The device contacts may be exposed at the front surface. A plurality of traces may overlie the microelectronic device. A conductive plane overlies a portion of the traces and is insulated therefrom. A first bond element electrically connects the at least one conductive plane with the at least one reference contact, wherein the at least one reference contact is connectable to a source of reference potential. A plurality of second bond elements is electrically connected to device contacts with the traces. The traces are electrically connected with the element contacts. Traces may have substantial portions spaced a fixed distance from the conductive plane and generally parallel to the conductive plane, such that a desired impedance is achieved for the traces.
In an embodiment of this aspect of the invention, the surface of the conductive plane is a surface facing away from the front surface of the microelectronic device.
In another embodiment, the substantial portion of each trace has a length that is at least 25% of the total length of each individual respective trace. Alternatively, substantial portions of the traces are lengths of at least 1 millimeter.
In another embodiment, the conductive plane is a power plane. Alternatively, the conductive plane is a ground plane. In yet another alternative embodiment, the conductive plane includes a first conductive plane being a power plane and a second conductive plane being a ground plane.
In still another embodiment of this aspect of the invention, the microelectronic device is a first microelectronic device and the assembly further includes a second microelectronic device. The second microelectronic device may have a front surface facing the substrate and rear surface facing the first microelectronic device. The microelectronic device may have contacts exposed at the front surface thereof.
In accordance with another aspect of the present invention, a method of forming a microelectronic assembly includes bonding a subassembly that includes a conductive plane, a plurality of traces and a dielectric layer separating the plane from the traces, to a front surface of a microelectronic element; forming first wirebonds electrically connecting traces on the subassembly with the device contacts; and forming second wirebonds electrically connecting the traces with element contacts on an interconnection element disposed below a rear surface that is opposite a front face of the microelectronic element.
In an alternative embodiment, contacts on the front surface of the microelectronic element are exposed beyond an edge of the subassembly.
In another embodiment, an outer edge of the subassembly is a peripheral edge bounding a major surface of the subassembly.
In still another embodiment, the subassembly further includes an aperture through which the device contacts are exposed, and an interior edge of the subassembly is an edge of the aperture. Alternatively, the subassembly may be a circuit panel.
In another embodiment, the dielectric layer is selected from a polymeric material or a composite material.
Further aspects of the invention provide systems which incorporate microelectronic structures according to the foregoing aspects of the invention, composite chips according to the foregoing aspects of the invention, or both in conjunction with other electronic devices. For example, the system may be disposed in a single housing, which may be a portable housing. Systems according to preferred embodiments in this aspect of the invention may be more compact than comparable conventional systems.
In one embodiment, microelectronic assembly 100 includes a microelectronic device 10 that is bonded the interconnection element by use of a bonding material, such as a dielectric adhesive 53. The microelectronic device may be further conductively connected to interconnection element 30 through a first plurality of device wires 65 and also conductively connected to a conductive plane 60 through a second plurality of reference wires 68. Microelectronic device 10 can be a single “bare”, i.e., unpackaged die, e.g., a semiconductor chip having microelectronic circuitry thereon. In alternative embodiments, microelectronic device 10 can include a packaged semiconductor die. Initially, a plurality of contacts 12 are exposed at a surface 28 of the microelectronic device 10. For example, a plurality of contacts 12 can be exposed at a contact-bearing surface of a semiconductor die and may be arranged in one or more rows exposed at such surface.
For ease of reference, directions are stated in this disclosure with reference to a “top”, i.e., contact-bearing surface 28 of a semiconductor chip or microelectronic device 10. Generally, directions referred to as “upward” or “rising from” shall refer to the direction orthogonal and away from the microelectronic device top surface 28. Directions referred to as “downward” shall refer to the directions orthogonal to the device top surface 128 and opposite the upward direction. A “vertical” direction shall refer to a direction orthogonal to the chip top surface. The term “above” a reference point shall refer to a point upward of the reference point, and the term “below” a reference point shall refer to a point downward of the reference point. The “top” of any individual element shall refer to the point or points of that element which extend furthest in the upward direction, and the term “bottom” of any element shall refer to the point or points of that element which extend furthest in the downward direction. It is to be further appreciated that like reference numerals will be used to describe like elements.
The wires 65,68 typically are not individually insulated, such as by insulating sheaths thereon. As seen in
Wirebonds can be formed with relatively precise placement and within desirable tolerances such that parallel, closely spaced runs can be achieved which run parallel to the surface 28 of the conductive plane 60. As used herein, “parallel” denotes a structure which is parallel to another structure within manufacturing tolerances. For example, wirebonding equipment available from Kulicke and Soffa can be used to achieve precision wirebonds. Thus, device wires 65 can be formed which have runs which are perfectly straight in lateral directions above the chip surface 28 and conductive plane 60 or are close to being straight. While such precision can be achieved in forming the wirebonds, nothing is meant to require precisely formed parallel, straight wirebonds other than as specifically recited in the appended claims.
In one embodiment, the conductive plane 60 overlies the microelectronic device 10 and may be positioned between the microelectronic device 10 and wires 65. The conductive plane 60 can be formed and attached to the microelectronic device 10 by any means known in the art. In one embodiment, the conductive plane may be laminated onto the surface of the microelectronic device 10. For example, the conductive plane 60 can be provided by pre-processing a metal sheet such as a copper foil, for example, to form openings 64 in the metal sheet. Then, the metal sheet can be bonded to the surface 28 of the microelectronic device, such as by using an adhesive 62. Alternatively, it may also be formed and attached to the surface of the microelectronic device by processing applied to the surface 28 of a microelectronic device 10 such as a metal deposition or plating process applied to the device while the device is in the form of a wafer or panel containing a plurality of connected devices or after the device has been singulated from other such devices.
In one embodiment, dimensions of the conductive plane in directions oriented horizontally with respect to the surface 28 of microelectronic device 10 can be smaller than corresponding dimensions of the microelectronic device surface 28. As seen in
A first set of wirebonds 65, also referred to hereinafter as “device wires” or “wires” connect the contacts 12 of the microelectronic device 10 with contacts 75 on the interconnection element 30. As seen in
In one embodiment, substantial portions x (
When the device wires are disposed in such relationship with a reference conductor such as conductive plane 60, signals to and from the microelectronic device may be transmitted with less noise entering the connections (e.g., wirebonds) carrying the signals. Each wirebond and the conductive plane, being tied to a source of reference voltage, form a transmission line structure that has a desired characteristic impedance.
In order to achieve a desired characteristic impedance, parameters can be selected such as the conductive properties of the metal used in the wire, as well as the shape and thickness of the wire, the thickness of the insulating material 50 between the wire and the conductive layer 60, the dielectric constant of the insulating material, i.e., permeability.
where H is the separation distance between the wire and the conductive plane, d is the diameter of the wire and ∈R is the permeability of the dielectric material that separates the wire from the conductive plane. The permeability ∈R can vary depending on the type of dielectric material used. The separation distance H is a factor which can be at least partly determined by the process used to fabricate the microelectronic assembly. The wire diameter may be at least partly determined by the process used to fabricate the microelectronic assembly.
In
As shown in
As shown in
As seen in
As best seen in
Referring now to the alternative embodiment of
As in the previous embodiments, device wires 65 may extend between the device contact 12 and element contacts 77 on the interconnection element 12. Additionally, reference wires 68 may extend as wirebonds from any of the conductive plane portions 102,104,106,108 to another device or contact internal or external to the microelectronic assembly 200. In the embodiment shown, reference wires 68E may extend between two conductive plane portions to help ensure that both conductive plane portions remain at a stable voltage despite temporary fluctuations in power demand or other transient effects. For example, reference wire 68E electrically connects conductive plane portion 102 and conductive plane portion 104, and reference wire 68E electrically connects conductive plane portions 106,108. Reference wires 68F may also electrically connect conductive plane portions 102,104,106,108 to respective reference contacts 77 on the interconnection element 30. One or more reference wires 68G may also extend between any of the conductive plane portions to a device contact 12. For example, as shown, a reference wire electrically connects a conductive plane portion 104 with a reference contact 77. In one embodiment, multiple reference wires 68G may extend between a conductive plane portion (e.g., conductive plane portion 104, as shown) and a single device contact 12.
In the exemplary embodiment shown, conductive plane portions 102,104 are ground planes and conductive plane portions 106,108 are power planes. The conductive plane portions 102,104 which are ground planes may be electrically connected to device contacts 12 serving as a ground reference therefor, and a ground reference contact 77 of the substrate, and to one another. Further connection of the ground planes 102,104 to a reference potential such as a system ground reference can be provided through terminals 40 of the microelectronic assembly 100 (
Referring to
In the embodiment shown, the conductive strips 80 are divided into two primary portions, a first upper portion 300 and a second lower portion 302. As shown, there are no supporting portions 82 extending between the first upper portion 300 and second lower portion 302, such that there is a natural division between the first upper portion 300 and second lower portion 302. As in the previous embodiments, reference wires 68E may extend between two conductive strips 80 in the first upper portion 300. Additionally, a reference wire 68F may extend from the conductive plane 80 in the first upper portion 300 to a reference contact 77 on the interconnection element 30. Similarly, reference wires 68E may extend between two conductive strips 80 in the second lower portion 302, as well as extend from the conductive strip 80 in the second lower portion 302 to a reference contact 77 on the interconnection element 30. Additionally, a reference wire 68G may extend from one of the conductive strips 82 to a contact 12 on the microelectronic device 10.
The foregoing embodiments have been described with respect to the interconnection of individual microelectronic devices, e.g., semiconductor chips. However, it is contemplated that the methods described herein may be employed in a wafer-scale manufacturing process applied simultaneously to a plurality of chips connected together at edges of the chips, such as a plurality of chips connected together at edges in form of a unit, panel, wafer or portion of a wafer.
Turning now to
As shown, the microelectronic device 10 may be bonded to the interconnection element 30 using known bonding materials, such as a dielectric adhesive 53. The conductive plane 60 may be directly attached or bonded to the microelectronic element 10 through a lamination process or other known processes, as previously described. The conductive plane 60 is positioned to overlie the microelectronic device 10, as well as traces 404 extending along the surface of the microelectronic device 10.
The traces 404 may be formed on the microelectronic device 10 by any suitable metal deposition technique. The traces 404 may be formed by depositing a primary metal layer, e.g., by sputtering, electroless deposition, etc. The primary metal layer can then be photolithographically patterned into separate traces 404, followed by electroplating to increase the thickness of the traces and if desired, form traces 404 having multiple different metal layers. Alternatively, the traces 404 may be formed from a metal layer deposited on the surface of the microelectronic device 10, which can then be selectively patterned using a subtractive process, such as etching. It is to be appreciated that it is preferable for the formation of the traces 404 to occur while the microelectronic device 10 is in its wafer form.
Device contacts 12 (shown in hidden line in
In this embodiment, substantial lengths of the traces 404 extend between and substantially parallel to the microelectronic device 10 and conductive plane 60. As the conductive plane 60 is a fixed height above the traces (and the traces 404 a fixed height below the conductive plane 60), a desired impedance can be obtained from this arrangement, based on the principles previously explained herein.
Reference wires 68 may extend from the conductive plane 60 to reference contacts 77 on the interconnection element 30. The reference wires 68 may be further connected to a source of reference potential such as ground or a power supply input terminal of the microelectronic assembly 400.
Referring to
As shown, the device contacts 12 respectively extend between conductive plane portion 410 and conductive plane portion 412, as well as between conductive plane portion 414 and conductive plane portion 416. Traces 404 extend substantially parallel to the conductive plane portions 410,412,414,416 and microelectronic device 10. Since the substantial lengths of the traces 404 extend a substantially constant distance from the conductive plane portions 410, 412, 414, and 416, a desired impedance can be obtained in accordance with previously discussed principles.
The conductive plane portions 410,412, may be ground planes and the conductive plane portions 414,416 may be power planes. As in the previous embodiments, there are numerous variations as to how the conductive portions 410,412,414,416 are connected to each other, reference contacts 77 on the interconnection element, or contacts 12 on the microelectronic device. In one embodiment, at least one reference wire 68F can extend from the ground conductive plane portions 410,412 to a reference contact 77 on the interconnection element 30. Another reference wire 68F′ can also extend from the power plane portions 414,416 to a reference contact 77 on the interconnection element 30. Additionally, at least one reference wire 68E can extend between the two conductive plane portions. For example, in one embodiment, reference wire 68E electrically connects the ground conductive plane portion 410 and ground conductive plane portion 412. Similarly, reference wire 68E electrically connects the ground conductive plane portion 410 and ground conductive plane portion 412. Furthermore, at least one reference wire 68G can connect a conductive plane portion 414 or 412, with a contact 12 on the microelectronic device. It is to be appreciated that any combination of the foregoing may be utilized in connection with the present embodiments. In one embodiment, an encapsulant 491 can be deposited around the microelectronic device 10, conductive plane 60, and wires 65,68. The microelectronic assembly 400 can then be connected via terminals 40, such as conductive pins or solder ball connections, to the contacts 489 of a circuit board 493 or other external device.
Referring now to
As shown, the second microelectronic device 10′ and second conductive plane 60′ are electrically connected to the interconnection element 30 in the same arrangement as the first microelectronic assembly 400 shown in
Turning now to
The microelectronic device 10 may be bonded to the interconnection element 30 using known bonding materials, such as a dielectric adhesive 53. The subassembly may be attached or bonded to the microelectronic device 10 using an adhesive layer 63 or B-stage polymer element which is then subsequently cured. In a particular embodiment, the subassembly can be a circuit panel fabricated according to typical circuit panel fabrication techniques. In particular examples, the dielectric layer can be made of polymeric material or be a composite material such as glass epoxy, such as FR4 or BT resin materials.
As best seen in
Typically, the subassembly is fabricated separately, and then assembled with the microelectronic device to form the assembly 500 shown. In a particular embodiment, the traces 504 may be formed by depositing a primary metal layer, e.g., by sputtering, electroless deposition, etc. The primary metal layer can then be photolithographically patterned into separate traces 504, followed by electroplating to increase the thickness of the traces and, if desired, form traces 504 having multiple different metal layers. Alternatively, the traces 504 may be formed from a metal layer deposited on the surface of the conductive plane 60, which can then be selectively patterned using a subtractive process, such as etching. It is to be appreciated that it is preferable for the formation of the traces 504 to occur while the microelectronic device 10 is in its wafer form.
Device contacts 12 are positioned along a central portion of the microelectronic device 10. As shown, traces 504 on the conductive plane 60 provide an electrical connection between the device contacts 12 and the contacts 75 exposed at the interconnection element 30. Device wires 68A extend from the device contacts 12 to contacts 502A. Device wires 68B extend beyond the edge of the microelectronic device 10 to further electrically connect the contacts 502B with element contacts 75 on the interconnection element 30. This provides for an electrical connection between the microelectronic device and the interconnection element 30 without requiring substantial lengths of the wires to extend across the top surface 514 of the conductive plane 60, as disclosed in the previous embodiments.
In this embodiment, substantial lengths of the traces 504 extend substantially parallel to the microelectronic device and conductive plane 60. As the traces 504 are a fixed height above the conductive plane 60, a desired impedance can be obtained from this arrangement, based on the principles previously explained herein.
Reference wires 65 may extend from the conductive plane 60 to reference contacts 77 on the interconnection element 30. The reference contacts 77 may be further connectable to a source of reference potential such as a ground terminal 40 or a power supply input terminal 40 of the microelectronic assembly 500, as described above.
An encapsulant 591 can be deposited over the traces 504, around the microelectronic device 10, conductive plane 60, device wires, reference wires, and openings. The microelectronic assembly 500 can then be connected via terminals 40 exposed at the interconnection element 30 to contacts 599 of a circuit board 595 or other external device.
Referring to
As shown, the device contacts 12 respectively extend between conductive plane portion 610 and conductive plane portion 612, as well as between conductive plane portion 614 and conductive plane portion 616. Therefore, some device contacts 12 are exposed beyond the edges 611 and 613 of conductive plane portions 610 and 612, respectively, and some device contacts 12 are exposed beyond edges 615,617 of plane portions 614,616. Traces 604 extend substantially parallel to the conductive plane portions 610, 612, 614, 616 and microelectronic device 10. Since the substantial lengths of the traces 604 extend a substantially constant distance from the conductive plane portions 610,612,614,616, a desired impedance can be obtained in accordance with previously discussed principles.
In one embodiment, the first and second conductive plane portions 610, 612 may be ground planes and the third and fourth conductive plane portions 614,616 are power planes. The first and third conductive plane portions 610,614 can provide ground and power connections for off-chip drivers, and the second and fourth conductive plane portions 612, 616 can provide ground and power connections for circuitry other than for the off-chip drivers. In such embodiments, the microelectronic device 10 is capable of driving these particular signals towards a circuit board. This is helpful to reduce noise that might otherwise be coupled from the power and ground connections to other circuitry of the chip. Such microelectronic elements may include logic chips, memory chips, e.g., DRAM, or various other types of chips. In this example, off-chip drivers for a DRAM can include data output buffers, data strobes.
As in the previous embodiments, there are numerous variations as to how the conductive portions 610,612,614,616 are connected to each other, as well as element contacts 75 and reference contacts 77 exposed at the interconnection element 30 or contacts 12 exposed at the microelectronic device 10. In one embodiment, at least one reference wire 68H can extend from the ground conductive plane portions 610, 612 to a reference contact 77 on the interconnection element 30. Another reference wire 68H′ can also extend from one or both of the power plane portions 614,616 to a reference contact 77 on the interconnection element 30. Additionally, at least one reference wire 68I can extend between the two conductive plane portions. For example, in one embodiment, reference wire 68I electrically connects the ground conductive plane portion 610 and ground conductive plane portion 612. Furthermore, at least one reference wire 68G can connect a conductive plane portion 610 or 612, with a contact 12 on the microelectronic device.
Referring now to
As shown in
As shown in
The ground bar 761 may be spaced apart from the conductive vias 767. The ground bar 761 may be an elongated strip of conductive material that extends adjacent the peripheral edges 769 of the conductive plane and is positioned between the conductive vias 767 and opposed peripheral edges 769 of the conductive plane 60. In an alternative embodiment, the conductive vias 767 may instead be positioned closer to the opposed peripheral edges 769 of the insulating layer 735 than the ground bar 761. The conductive vias 767 may also be formed to have a bondable surface at the first surface of the dielectric layer, so as to obviate the need for a ground bar 761 or ground ring 763. A ground ring 763, when present, may be formed similar to the ground bar, the only difference being that the ground ring 763 is in the shape of a ring. Traces 704 may also be used to electrically connect the ground bar 761 and ground ring 763 to the conductive vias 767.
In a particular embodiment, as shown in
As best shown in
Terminals 798 exposed at the interconnection element 30 may be used to electrically connect the interconnection element 30 with another device. In one example, solder balls 797 are used to electrically connect terminals with contacts on a circuit board. A bonding material, such as solder balls, may be used to provide an external connection to contacts 799 of another device, such as a circuit board 795 (see
The modifications shown in
Device contacts 12 are positioned along a central portion of the first microelectronic device 10 and exposed between peripheral edges 810 of the microelectronic device 10 and the outer edge 812 of the conductive plane 60. As shown, traces 804 exposed at the front surface 28 of microelectronic device 10 provide an electrical connection between the contacts 802 and the device contacts 12. Device wires 65 extend beyond the edge of the microelectronic device 10 to further electrically connect the contacts 802 with element contacts 75 on the interconnection element 30. This provides for an electrical connection between the microelectronic device 10 and the interconnection element 30 without requiring substantial lengths of the wires to extend across the top surface 814 of the conductive plane 60, as disclosed in the previous embodiments.
As shown in
An encapsulant 891 can be deposited around the microelectronic device 10, conductive plane 60, bond wires, and openings. The microelectronic assembly 800 can then be connected via terminals 40 exposed at the interconnection element 30 to contacts 899 of a circuit board 895 or other external device.
In this embodiment, substantial lengths of the redistribution traces 804 extend between and substantially parallel to the microelectronic device 10 and conductive plane 60. As the conductive plane 60 is a fixed height above the conductive traces (and the conductive traces 804 a fixed height below the conductive plane 60), a desired impedance can be obtained from this arrangement, based on the principles previously explained herein.
The various microelectronic assemblies discussed in each of the embodiments above can be utilized in construction of diverse electronic systems. For example, referring to
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
The present application is a continuation-in-part of U.S. Pat. No. 12/883,821, filed on Sep. 16, 2010, the disclosure of which is incorporated herein by reference.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4680613 | Daniels et al. | Jul 1987 | A |
| 4980753 | Dunaway et al. | Dec 1990 | A |
| 5028983 | Bickford et al. | Jul 1991 | A |
| 5065282 | Polonio | Nov 1991 | A |
| 5343074 | Higgins, III et al. | Aug 1994 | A |
| 5394010 | Tazawa et al. | Feb 1995 | A |
| 5468999 | Lin et al. | Nov 1995 | A |
| 5471151 | DiFrancesco | Nov 1995 | A |
| 5523621 | Kikuchi | Jun 1996 | A |
| 5552631 | McCormick | Sep 1996 | A |
| 5606196 | Lee et al. | Feb 1997 | A |
| 5638596 | McCormick | Jun 1997 | A |
| 5639989 | Higgins, III | Jun 1997 | A |
| 5835988 | Ishii | Nov 1998 | A |
| 5880403 | Czajkowski et al. | Mar 1999 | A |
| 6001671 | Fjelstad | Dec 1999 | A |
| 6326678 | Karnezos et al. | Dec 2001 | B1 |
| 6445594 | Nakagawa et al. | Sep 2002 | B1 |
| 6476506 | O'Connor et al. | Nov 2002 | B1 |
| 6518659 | Glenn | Feb 2003 | B1 |
| 6538336 | Secker et al. | Mar 2003 | B1 |
| 6552417 | Combs | Apr 2003 | B2 |
| 6667546 | Huang et al. | Dec 2003 | B2 |
| 6770822 | Pasternak et al. | Aug 2004 | B2 |
| 6812580 | Wenzel et al. | Nov 2004 | B1 |
| 7166495 | Ball | Jan 2007 | B2 |
| 7205651 | Do et al. | Apr 2007 | B2 |
| 7217997 | Wyland | May 2007 | B2 |
| 7303113 | Kwark et al. | Dec 2007 | B2 |
| 7450110 | Shahoian et al. | Nov 2008 | B2 |
| 7456505 | Gospodinova et al. | Nov 2008 | B2 |
| 7466021 | Fjelstad | Dec 2008 | B2 |
| 7468560 | Guengerich et al. | Dec 2008 | B2 |
| 7528011 | Yano et al. | May 2009 | B2 |
| 7537962 | Jang et al. | May 2009 | B2 |
| 7550842 | Khandros et al. | Jun 2009 | B2 |
| 7723852 | Kim et al. | May 2010 | B1 |
| 7727801 | Saran | Jun 2010 | B2 |
| 7768135 | St. Amand et al. | Aug 2010 | B1 |
| 7843021 | Zhe et al. | Nov 2010 | B2 |
| 7855463 | Brox et al. | Dec 2010 | B2 |
| 7875985 | Hiller et al. | Jan 2011 | B2 |
| 7923851 | Haba et al. | Apr 2011 | B2 |
| 8026129 | Cablao et al. | Sep 2011 | B2 |
| 8222725 | Haba et al. | Jul 2012 | B2 |
| 8237250 | Chang Chien et al. | Aug 2012 | B2 |
| 8243465 | Itaya et al. | Aug 2012 | B2 |
| 8253258 | Sonobe et al. | Aug 2012 | B2 |
| 8294249 | Pilling et al. | Oct 2012 | B2 |
| 8531043 | Ha et al. | Sep 2013 | B2 |
| 8575766 | Haba et al. | Nov 2013 | B2 |
| 20010015490 | Lee | Aug 2001 | A1 |
| 20030090001 | Beatson et al. | May 2003 | A1 |
| 20040164389 | Lee | Aug 2004 | A1 |
| 20040238939 | Wu | Dec 2004 | A1 |
| 20050006742 | Sugiyama et al. | Jan 2005 | A1 |
| 20050045378 | Heng et al. | Mar 2005 | A1 |
| 20050098870 | Thomas et al. | May 2005 | A1 |
| 20050116013 | Kwark et al. | Jun 2005 | A1 |
| 20060049505 | Wyland | Mar 2006 | A1 |
| 20060102992 | Kwon et al. | May 2006 | A1 |
| 20060125079 | Wyland et al. | Jun 2006 | A1 |
| 20060131742 | Tzu | Jun 2006 | A1 |
| 20060145308 | Floyd et al. | Jul 2006 | A1 |
| 20060175712 | Lyn et al. | Aug 2006 | A1 |
| 20060180916 | Wyland | Aug 2006 | A1 |
| 20070007644 | Zhao et al. | Jan 2007 | A1 |
| 20070034674 | Mii et al. | Feb 2007 | A1 |
| 20070105272 | Lee et al. | May 2007 | A1 |
| 20070148821 | Do et al. | Jun 2007 | A1 |
| 20070170601 | Miyaki et al. | Jul 2007 | A1 |
| 20070284716 | Vindasius et al. | Dec 2007 | A1 |
| 20080088012 | Ohkawa | Apr 2008 | A1 |
| 20080111248 | Foong et al. | May 2008 | A1 |
| 20090032973 | Sasaki et al. | Feb 2009 | A1 |
| 20090057862 | Ha et al. | Mar 2009 | A1 |
| 20090256266 | Lao et al. | Oct 2009 | A1 |
| 20100230828 | Haba et al. | Sep 2010 | A1 |
| 20100232128 | Haba et al. | Sep 2010 | A1 |
| 20100270667 | Tong et al. | Oct 2010 | A1 |
| 20120068317 | Haba et al. | Mar 2012 | A1 |
| 20120068338 | Haba et al. | Mar 2012 | A1 |
| 20120068361 | Haba | Mar 2012 | A1 |
| Number | Date | Country |
|---|---|---|
| 101410974 | Apr 2009 | CN |
| 0915504 | May 1999 | EP |
| 1770777 | Apr 2007 | EP |
| 06-268100 | Sep 1994 | JP |
| 7058138 | Mar 1995 | JP |
| 9-027512 | Jan 1997 | JP |
| 2000021926 | Jan 2000 | JP |
| 2000332160 | Nov 2000 | JP |
| 2001007140 | Jan 2001 | JP |
| 2001339016 | Dec 2001 | JP |
| 2004112143 | Apr 2004 | JP |
| 2006216823 | Aug 2006 | JP |
| 100270817 | Nov 2000 | KR |
| 20050002659 | Jan 2005 | KR |
| 100702970 | Jan 2007 | KR |
| 100935854 | Jan 2010 | KR |
| 100950511 | Mar 2010 | KR |
| 2005010989 | Feb 2005 | WO |
| 2008008948 | Jan 2008 | WO |
| 2010020836 | Feb 2010 | WO |
| Entry |
|---|
| Taiwan Office Action for Application No. 099107377 dated Feb. 18, 2013. |
| International Search Report Application No. PCT/US2010/027135, dated Aug. 30, 2011. |
| International Search Report, PCT/US2010/027141, dated Jan. 6, 2012. |
| Partial International Search Report and Invitation to Pay Additional Fees, PCT/US2010/027135, dated Mar. 21, 2011. |
| Partial International Search Report and Invitation to Pay Additional Fees, PCT/US2010/027141, dated Jan. 27, 2011. |
| U.S. Appl. No. 12/883,556. |
| U.S. Appl. No. 12/883,612. |
| U.S. Appl. No. 12/883,811. |
| U.S. Appl. No. 12/883,821. |
| Japanese Office Action for Application No. 2011-554234 dated Jul. 12, 2013. |
| Chinese Office Action for Application No. 201080020828.3 dated Jul. 29, 2013. |
| Chinese Office Action for Application No. 201080020851.2 dated Nov. 28, 2013. |
| Japanese Office Action for Application No. 2011-554232 dated Feb. 4, 2014. |
| Chinese Office Action for Application No. 201080020828.3 dated Mar. 3, 2014. |
| Number | Date | Country | |
|---|---|---|---|
| 20120313228 A1 | Dec 2012 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12883821 | Sep 2010 | US |
| Child | 13472081 | US |
