Phillip F. CHAPMAN

Person

Colchester, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Structure and method of latchup robustness with placement of throug...
- Patent number 10,978,452
- Issue date Apr 13, 2021
- International Business Machines Corporation
- Phillip F. Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of latchup robustness with placement of throug...
- Patent number 10,170,476
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Phillip F. Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of latchup robustness with placement of throug...
- Patent number 9,842,838
- Issue date Dec 12, 2017
- International Business Machines Corporation
- Phillip F. Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of latchup robustness with placement of throug...
- Patent number 9,397,010
- Issue date Jul 19, 2016
- International Business Machines Corporation
- Phillip F. Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of latchup robustness with placement of throug...
- Patent number 9,275,997
- Issue date Mar 1, 2016
- International Business Machines Corporation
- Phillip F. Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Segmented guard ring structures with electrically insulated gap str...
- Patent number 8,987,067
- Issue date Mar 24, 2015
- International Business Machines Corporation
- Robert L. Barry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of latchup robustness with placement of throug...
- Patent number 8,853,789
- Issue date Oct 7, 2014
- International Business Machines Corporation
- Phillip F. Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of latchup robustness with placement of throug...
- Patent number 8,420,518
- Issue date Apr 16, 2013
- International Business Machines Corporation
- Phillip F. Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bias-controlled deep trench substrate noise isolation integrated ci...
- Patent number 8,212,332
- Issue date Jul 3, 2012
- International Business Machines Corporation
- Phillip Francis Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bias-controlled deep trench substrate noise isolation integrated ci...
- Patent number 8,021,941
- Issue date Sep 20, 2011
- International Business Machines Corporation
- Phillip Francis Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of latchup robustness with placement of throug...
- Patent number 8,017,471
- Issue date Sep 13, 2011
- International Business Machines Corporation
- Phillip F. Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for a latchup robust array I/O using through wafer via
- Patent number 7,855,420
- Issue date Dec 21, 2010
- International Business Machines Corporation
- Phillip Francis Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Latchup robust array I/O using through wafer via
- Patent number 7,741,681
- Issue date Jun 22, 2010
- International Business Machines Corporation
- Phillip Francis Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for a latchup robust gate array using through wafer via
- Patent number 7,696,541
- Issue date Apr 13, 2010
- International Business Machines Corporation
- Phillip Francis Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Design methodology of guard ring design resistance optimization for...
- Patent number 7,549,135
- Issue date Jun 16, 2009
- International Business Machines Corporation
- Phillip F. Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latchup robust gate array using through wafer via
- Patent number 7,498,622
- Issue date Mar 3, 2009
- International Business Machines Corporation
- Phillip Francis Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor and method of fabricating
- Patent number 6,391,661
- Issue date May 21, 2002
- International Business Machines, Corp.
- Daniel S. Brooks
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor and method of fabricating
- Patent number 6,229,155
- Issue date May 8, 2001
- International Business Machines Corporation
- Daniel S. Brooks
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...
- Publication number 20190081046
- Publication date Mar 14, 2019
- International Business Machines Corporation
- Phillip F. CHAPMAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...
- Publication number 20180040619
- Publication date Feb 8, 2018
- International Business Machines Corporation
- Phillip F. CHAPMAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...
- Publication number 20160268258
- Publication date Sep 15, 2016
- International Business Machines Corporation
- Phillip F. CHAPMAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...
- Publication number 20160126147
- Publication date May 5, 2016
- International Business Machines Corporation
- Phillip F. CHAPMAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STR...
- Publication number 20150035112
- Publication date Feb 5, 2015
- International Business Machines Corporation
- Robert L. Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...
- Publication number 20140367792
- Publication date Dec 18, 2014
- Phillip F. CHAPMAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STR...
- Publication number 20140246752
- Publication date Sep 4, 2014
- International Business Machines Corporation
- Robert L. Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...
- Publication number 20130154024
- Publication date Jun 20, 2013
- International Business Machines Corporation
- Phillip F. CHAPMAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CI...
- Publication number 20110291238
- Publication date Dec 1, 2011
- International Business Machines Corporation
- Phillip Francis Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...
- Publication number 20110198703
- Publication date Aug 18, 2011
- International Business Machines Corporation
- Phillip F. CHAPMAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CI...
- Publication number 20110018094
- Publication date Jan 27, 2011
- International Business Machines Corporation
- Phillip Francis Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...
- Publication number 20100032767
- Publication date Feb 11, 2010
- Phillip F. Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DESIGN METHODOLOGY FOR GUARD RING DESIGN RESISTANCE OPTIMIZATION FO...
- Publication number 20090166798
- Publication date Jul 2, 2009
- International Business Machines Corporation
- Phillip F. Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LATCHUP ROBUST ARRAY I/O USING THROUGH WAFER VIA
- Publication number 20090152632
- Publication date Jun 18, 2009
- Phillip Francis Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE FOR A LATCHUP ROBUST GATE ARRAY USING THROUGH WAFER VIA
- Publication number 20090152593
- Publication date Jun 18, 2009
- Phillip Francis Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE FOR A LATCHUP ROBUST ARRAY I/O USING THROUGH WAFER VIA
- Publication number 20090152592
- Publication date Jun 18, 2009
- Phillip Francis Chapman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DESIGN METHODOLOGY OF GUARD RING DESIGN RESISTANCE OPTIMIZATION FOR...
- Publication number 20080134104
- Publication date Jun 5, 2008
- International Business Machines Corporation
- Phillip F. Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor and method of fabricating
- Publication number 20010016362
- Publication date Aug 23, 2001
- International Business Machines Corporation
- Daniel S. Brooks
- H01 - BASIC ELECTRIC ELEMENTS

Phillip F. CHAPMAN

Person

Patents Grantslast 30 patents

Structure and method of latchup robustness with placement of throug...

Structure and method of latchup robustness with placement of throug...

Structure and method of latchup robustness with placement of throug...

Structure and method of latchup robustness with placement of throug...

Structure and method of latchup robustness with placement of throug...

Segmented guard ring structures with electrically insulated gap str...

Structure and method of latchup robustness with placement of throug...

Structure and method of latchup robustness with placement of throug...

Bias-controlled deep trench substrate noise isolation integrated ci...

Bias-controlled deep trench substrate noise isolation integrated ci...

Structure and method of latchup robustness with placement of throug...

Structure for a latchup robust array I/O using through wafer via

Latchup robust array I/O using through wafer via

Structure for a latchup robust gate array using through wafer via

Design methodology of guard ring design resistance optimization for...

Latchup robust gate array using through wafer via

Semiconductor and method of fabricating

Semiconductor and method of fabricating

Patents Applicationslast 30 patents

STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...

STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...

STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...

STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...

SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STR...

STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...

SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STR...

STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...

BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CI...

STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...

BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CI...

STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUG...

DESIGN METHODOLOGY FOR GUARD RING DESIGN RESISTANCE OPTIMIZATION FO...

LATCHUP ROBUST ARRAY I/O USING THROUGH WAFER VIA

STRUCTURE FOR A LATCHUP ROBUST GATE ARRAY USING THROUGH WAFER VIA

STRUCTURE FOR A LATCHUP ROBUST ARRAY I/O USING THROUGH WAFER VIA

DESIGN METHODOLOGY OF GUARD RING DESIGN RESISTANCE OPTIMIZATION FOR...

Semiconductor and method of fabricating