Pierre Maillard

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for SEU detection and correction
- Patent number 12,346,226
- Issue date Jul 1, 2025
- Xilinx, Inc.
- Kumar Rahul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Designing single event upset latches
- Patent number 11,652,481
- Issue date May 16, 2023
- Xilinx, Inc.
- Pierre Maillard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single event latch-up (SEL) mitigation detect and mitigation
- Patent number 10,958,067
- Issue date Mar 23, 2021
- Xilinx, Inc.
- Pierre Maillard
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Single event latch-up (SEL) mitigation techniques
- Patent number 10,861,848
- Issue date Dec 8, 2020
- Xilinx, Inc.
- Michael J. Hart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit for and method of storing data in an integrated circuit device
- Patent number 10,574,214
- Issue date Feb 25, 2020
- Xilinx, Inc.
- Pierre Maillard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single event upset (SEU) mitigation for FinFET technology using fin...
- Patent number 10,366,999
- Issue date Jul 30, 2019
- Xilinx, Inc.
- Pierre Maillard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit for and method of storing data in an integrated circuit device
- Patent number 10,263,623
- Issue date Apr 16, 2019
- Xilinx Inc.
- Yanran Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for and method of enabling the selection of a circuit
- Patent number 10,033,388
- Issue date Jul 24, 2018
- Xilinx, Inc.
- Mini Rawat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for and method of preventing multi-bit upsets induced by si...
- Patent number 9,825,632
- Issue date Nov 21, 2017
- Xilinx, Inc.
- Pierre Maillard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mitigation of single event latchup
- Patent number 9,793,899
- Issue date Oct 17, 2017
- Xilinx, Inc.
- Pierre Maillard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Selection of logic paths for redundancy
- Patent number 9,484,919
- Issue date Nov 1, 2016
- Xilinx, Inc.
- Praful Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Master-slave flip-flops and methods of implementing master-slave fl...
- Patent number 9,281,807
- Issue date Mar 8, 2016
- Xilinx, Inc.
- Pierre Maillard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit package with thermal neutron shielding
- Patent number 9,236,354
- Issue date Jan 12, 2016
- Xilinx, Inc.
- Pierre Maillard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single-event upset mitigation in circuit design for programmable in...
- Patent number 9,183,338
- Issue date Nov 10, 2015
- Xilinx, Inc.
- Praful Jain
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR SEU DETECTION AND CORRECTION
- Publication number 20250117298
- Publication date Apr 10, 2025
- Xilinx, Inc.
- Kumar RAHUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGNING SINGLE EVENT UPSET LATCHES
- Publication number 20230055458
- Publication date Feb 23, 2023
- Xilinx, Inc.
- Pierre MAILLARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE EVENT LATCH-UP (SEL) MITIGATION DETECT AND MITIGATION
- Publication number 20200091713
- Publication date Mar 19, 2020
- Xilinx, Inc.
- Pierre Maillard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SINGLE EVENT LATCH-UP (SEL) MITIGATION TECHNIQUES
- Publication number 20200066713
- Publication date Feb 27, 2020
- Xilinx, Inc.
- Michael J. Hart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE EVENT UPSET (SEU) MITIGATION FOR FINFET TECHNOLOGY USING FIN...
- Publication number 20170287919
- Publication date Oct 5, 2017
- Xilinx, Inc.
- Pierre Maillard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH THERMAL NEUTRON SHIELDING
- Publication number 20150348915
- Publication date Dec 3, 2015
- Xilinx, Inc.
- Pierre Maillard
- H01 - BASIC ELECTRIC ELEMENTS

Pierre Maillard

Person

Patents Grantslast 30 patents

System and method for SEU detection and correction

Designing single event upset latches

Single event latch-up (SEL) mitigation detect and mitigation

Single event latch-up (SEL) mitigation techniques

Circuit for and method of storing data in an integrated circuit device

Single event upset (SEU) mitigation for FinFET technology using fin...

Circuit for and method of storing data in an integrated circuit device

Circuit for and method of enabling the selection of a circuit

Circuit for and method of preventing multi-bit upsets induced by si...

Mitigation of single event latchup

Selection of logic paths for redundancy

Master-slave flip-flops and methods of implementing master-slave fl...

Integrated circuit package with thermal neutron shielding

Single-event upset mitigation in circuit design for programmable in...

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR SEU DETECTION AND CORRECTION

DESIGNING SINGLE EVENT UPSET LATCHES

SINGLE EVENT LATCH-UP (SEL) MITIGATION DETECT AND MITIGATION

SINGLE EVENT LATCH-UP (SEL) MITIGATION TECHNIQUES

SINGLE EVENT UPSET (SEU) MITIGATION FOR FINFET TECHNOLOGY USING FIN...

INTEGRATED CIRCUIT PACKAGE WITH THERMAL NEUTRON SHIELDING