Prabhakar P. Tripathi

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low via resistance system
- Patent number 6,893,962
- Issue date May 17, 2005
- LSI Logic Corporation
- Prabhakar P. Tripathi
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of forming metal fuses in CMOS processes with copper interco...
- Patent number 6,828,653
- Issue date Dec 7, 2004
- LSI Logic Corporation
- Ruggero Castagnetti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming metal fuses in CMOS processes with copper interco...
- Patent number 6,664,141
- Issue date Dec 16, 2003
- LSI Logic Corporation
- Ruggero Castagnetti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low via resistance system
- Patent number 6,569,751
- Issue date May 27, 2003
- LSI Logic Corporation
- Prabhakar P. Tripathi
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method for adjusting the density of lines and contact openings acro...
- Patent number 6,109,775
- Issue date Aug 29, 2000
- LSI Logic Corporation
- Prabhakar P. Tripathi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a high electromigration resistant metallization s...
- Patent number 5,776,831
- Issue date Jul 7, 1998
- LSI Logic Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for improving patterning design for processing
- Patent number 5,654,897
- Issue date Aug 5, 1997
- LSI Logic Corporation
- Prabhakar P. Tripathi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and structure for improving patterning design for processing
- Patent number 5,477,466
- Issue date Dec 19, 1995
- LSI Logic Corporation
- Prabhakar P. Tripathi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and structure for improving patterning design for processing
- Patent number 5,379,233
- Issue date Jan 3, 1995
- LSI Logic Corporation
- Prabhakar P. Tripathi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Low via resistance system
- Publication number 20030203622
- Publication date Oct 30, 2003
- LSI Logic Corporation
- Prabhakar P. Tripathi
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Prabhakar P. Tripathi

Person

Patents Grantslast 30 patents

Low via resistance system

Method of forming metal fuses in CMOS processes with copper interco...

Method of forming metal fuses in CMOS processes with copper interco...

Low via resistance system

Method for adjusting the density of lines and contact openings acro...

Method of forming a high electromigration resistant metallization s...

Method and structure for improving patterning design for processing

Method and structure for improving patterning design for processing

Method and structure for improving patterning design for processing

Patents Applicationslast 30 patents

Low via resistance system