Pradeep Raj

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
High-speed multi-port memory supporting collision
- Patent number 12,183,393
- Issue date Dec 31, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Power supply circuit with reduced leakage current
- Patent number 12,047,073
- Issue date Jul 23, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory circuit architecture with multiplexing between memory banks
- Patent number 12,020,766
- Issue date Jun 25, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory write assist with reduced switching power
- Patent number 12,020,746
- Issue date Jun 25, 2024
- QUALCOMM Incorporated
- Rejeesh Ammanath Vijayan
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed multi-port memory supporting collision
- Patent number 11,955,169
- Issue date Apr 9, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with efficient DVS controlled by asynchronous inputs
- Patent number 11,837,313
- Issue date Dec 5, 2023
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Write assist circuitry for memory
- Patent number 11,049,552
- Issue date Jun 29, 2021
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Area efficient write data path circuit for SRAM yield enhancement
- Patent number 10,867,668
- Issue date Dec 15, 2020
- QUALCOMM Incorporated
- Sharad Kumar Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM write yield enhancement with pull-up strength modulation
- Patent number 10,811,086
- Issue date Oct 20, 2020
- QUALCOMM Incorporated
- Shiba Narayan Mohanty
- G11 - INFORMATION STORAGE
Information Patent Grant
Access assist with wordline adjustment with tracking cell
- Patent number 10,811,088
- Issue date Oct 20, 2020
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Write driver circuitry to reduce leakage of negative boost charge
- Patent number 9,916,892
- Issue date Mar 13, 2018
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Write data path to reduce charge leakage of negative boost
- Patent number 9,865,337
- Issue date Jan 9, 2018
- QUALCOMM Incorporated
- Fahad Ahmed
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture to improve write-ability in SRAM
- Patent number 9,721,650
- Issue date Aug 1, 2017
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Read-write contention circuitry
- Patent number 9,478,278
- Issue date Oct 25, 2016
- ARM Limited
- Rejeesh Ammanath Vijayan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS
- Publication number 20240312496
- Publication date Sep 19, 2024
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION
- Publication number 20240221828
- Publication date Jul 4, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS
- Publication number 20230290387
- Publication date Sep 14, 2023
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Write Assist with Reduced Switching Power
- Publication number 20230267993
- Publication date Aug 24, 2023
- QUALCOMM Incorporated
- Rejeesh Ammanath Vijayan
- G11 - INFORMATION STORAGE
Information Patent Application
POWER SUPPLY CIRCUIT WITH REDUCED LEAKAGE CURRENT
- Publication number 20230179183
- Publication date Jun 8, 2023
- QUALCOMM Incorporated
- Pradeep RAJ
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY WITH EFFICIENT DVS CONTROLLED BY ASYNCHRONOUS INPUTS
- Publication number 20230139283
- Publication date May 4, 2023
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION
- Publication number 20220310156
- Publication date Sep 29, 2022
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
ACCESS ASSIST WITH WORDLINE ADJUSTMENT WITH TRACKING CELL
- Publication number 20200294580
- Publication date Sep 17, 2020
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Application
AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT
- Publication number 20190108872
- Publication date Apr 11, 2019
- QUALCOMM Incorporated
- Sharad Kumar GUPTA
- G11 - INFORMATION STORAGE
Information Patent Application
Read-Write Contention Circuitry
- Publication number 20160293247
- Publication date Oct 6, 2016
- ARM Limited
- Rejeesh Ammanath Vijayan
- G11 - INFORMATION STORAGE

Pradeep Raj

Person

Patents Grantslast 30 patents

High-speed multi-port memory supporting collision

Power supply circuit with reduced leakage current

Memory circuit architecture with multiplexing between memory banks

Memory write assist with reduced switching power

High-speed multi-port memory supporting collision

Memory with efficient DVS controlled by asynchronous inputs

Write assist circuitry for memory

Area efficient write data path circuit for SRAM yield enhancement

SRAM write yield enhancement with pull-up strength modulation

Access assist with wordline adjustment with tracking cell

Write driver circuitry to reduce leakage of negative boost charge

Write data path to reduce charge leakage of negative boost

Architecture to improve write-ability in SRAM

Read-write contention circuitry

Patents Applicationslast 30 patents

MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS

HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION

MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS

Memory Write Assist with Reduced Switching Power

POWER SUPPLY CIRCUIT WITH REDUCED LEAKAGE CURRENT

MEMORY WITH EFFICIENT DVS CONTROLLED BY ASYNCHRONOUS INPUTS

HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION

ACCESS ASSIST WITH WORDLINE ADJUSTMENT WITH TRACKING CELL

AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT

Read-Write Contention Circuitry