Patent Application
20250218506
The present application relates generally to memories and, more specifically, to a serial read write memory with time multiplexed cleanup and write operations.
Modern processors often have multiple cores in which each core may read and write to a memory. Should the various cores have to share a single access port for both read and write operations to a memory, the computing speed may be affected due to collisions between the cores at the common access port. Multi-port memories have thus been developed that have separate read and write ports.
Although the inclusion of separate read and write ports is advantageous with respect to memory access, the access transistors, word line, and bit line(s) for each port increase the memory complexity and demand more die space on the semiconductor die in which the memory is integrated. Pseudo-dual-port (PDP) memories have thus been developed in which a common access port is first treated as a separate read port and then as a separate write port during a single memory clock cycle. Should the read and write operations occur to the same word line, the word line is first asserted for the read operation, discharged, and then asserted for the write operation. This repeated pulsing of the word line may also be denoted as a “double pumped” operation.
In accordance with an aspect of the disclosure, a serial read write memory is provided that includes: a bank of bitcells arranged into a plurality of columns, wherein the plurality of columns includes a multiplexed group of columns; a write column multiplexer configured to select for a write-selected column from the multiplexed group of columns during a write operation, wherein the multiplexed group of columns includes a write-unselected column; a first precharge circuit configured to charge a first pair of bit lines in the write-selected column to a memory power supply voltage responsive to an assertion of a first bit line precharge signal; and a second precharge circuit configured to charge a second pair of bit lines in the write-unselected column to the memory power supply voltage responsive to an assertion of a second bit line precharge signal.
In accordance with another aspect of the disclosure, a method of operation for a serial read write memory is provided that includes: performing a read operation to a multiplexed group of columns during a first portion of a memory clock cycle, wherein the multiplexed group of columns includes a write-selected column and an at least one write-unselected column, and wherein the memory clock cycle is divided into the first portion and a second portion; selecting for the write-selected column through a write column multiplexer to couple a bitcell in the write-selected column to a write driver in response to a termination of the first portion of the memory clock cycle while precharging a pair of bit lines in the at least one write-unselected column; and writing to a bitcell in the write-selected column using the write driver during the second portion of the memory clock cycle.
In accordance with yet another aspect of the disclosure, a pseudo-dual-port memory is provided that includes: a bank of bitcells arranged into a plurality of columns and into a plurality of rows, wherein the pseudo-dual-port memory is configured to assert a word line voltage for one of the rows during a read operation to the bank of bitcells in a first portion of a memory clock cycle and to assert the word line voltage during a write operation to a write-selected column in the plurality of columns in a second portion of the memory clock cycle; and a precharge generation circuit configured to control a precharge of each column prior to the read operation and to prevent a precharge of the write-selected column during the memory clock cycle.
Finally, in accordance with another aspect of the disclosure, a method of operation for a serial read write memory is provided that includes: discharging a first bit line in a write-selected column from a pre-charged state to a partially-discharged state during a read operation in a first portion of a memory clock cycle; and fully discharging the first bit line from the partially-discharged state to ground during a write operation in a second portion of the memory clock cycle.
These and other advantageous features may be better appreciated through the following detailed description.
Implementations of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.
Enhanced serial read write memories are disclosed with increased operating speed and reduced power consumption. Before discussing these memories in more detail, some memory concepts will first be discussed. A memory such as a static random-access memory (SRAM) typically includes many bitcells that are arranged into rows and columns. A word line traverses each row of bitcells. Similarly, a pair of bit lines traverses each column of bitcells. Should the rows and columns be organized into a single array, the corresponding word line and bit lines must be relatively long, which increases capacitance and can slow memory operation. It is thus traditional for the bitcells to be organized into banks, each bank having its own columns and rows. Should the bitcells in each bank be pseudo-dual-port bitcells, the resulting memory may be referred to as a serial read write memory in that a read operation is followed by a write operation in a single memory clock cycle.
During the read operation, sense amplifiers sense the voltage differences to read the binary contents stored in the accessed bitcells. Each sense amplifier occupies a certain amount of space on the semiconductor die. With respect to the integration into the semiconductor die, the columns are spaced apart from each other according to a column pitch that may be too small to accommodate a sense amplifier. It is thus traditional that the columns are arranged into multiplexed groups, with each group being multiplexed by a corresponding read column multiplexer and a corresponding write column multiplexer. The number of columns multiplexed by each read column multiplexer (MUX) and each write column multiplexer depends upon the implementation. For example, in a “MUX2” memory, each column multiplexer selects from a group of two columns. Similarly, each column multiplexer selects from a group of four columns in a “MUX4” memory, and so on. For simplicity, the following discussion will be directed to a “MUX2” implementation in which each column multiplexer selects from a group of two columns. However, it will be appreciated that other magnitudes of column multiplexing may be used in alternative implementations of the enhanced serial read write memories disclosed herein.
As used herein, a “serial read write memory” is defined as a memory in which a read operation to a bank may be followed by a write operation to the bank during a single memory clock cycle. During the read operation to a bank, a voltage difference develops across the bit line pair in each column. Prior to the write operation, it is thus traditional for a serial read write memory to perform a bit line pre-charge to pre-charge the bit lines to a memory power supply voltage. The pre-charge operation between the read and write operations may also be denoted as a cleanup operation since is “cleans up” the bit line voltage differences. In the write operation to a bank, each write column multiplexer selects for a column. The selected column is denoted herein as a write-selected column. The remaining columns in each group of multiplexed columns are denoted as write-unselected columns. During the write operation, a bit line in the selected column is discharged while the remaining bit line for the selected column remains charged to the memory power supply voltage. With the discharge completed, the discharge is maintained for a sufficient amount of time denoted as a write margin so that the accessed bitcell may be written to.
Should a read operation occur to a multiplexed group of columns in a bank followed by a write operation to the multiplexed group of columns during a memory clock cycle, the advantageous enhanced serial read write memories disclosed herein do not pre-charge the bit lines in the write-selected column following the read operation. Instead, the write operation may begin during what would have been the cleanup operation. In the write operation, one of the bit lines will be discharged in the write-selected column. Should the read operation have already partially discharged that bit line, no charge is spent pre-charging the bit line back to the memory power supply voltage only to then discharge it during the write operation. Moreover, even if the binary value to be written is such that the partially-discharged bit line must be charged to the memory power supply voltage during the write operation, the net effect is not only a power consumption reduction but also an increase in operating speed since the write operation is beginning during what would have been the cleanup operation in a traditional serial read write memory.
To provide a better appreciation of the advantages of the enhanced serial read write memories disclosed herein, an example multiplexed group of columns 100 for a bank in a traditional serial read write memory is shown in
The bitcells in the multiplexed group of columns 100 are arranged into N rows, where N is a plural positive integer. For illustration clarity, only a zeroth row and an (N−1)th row are shown in
The read operation may be to either the write-selected column or the write-unselected column. Prior to the read operation beginning at time t0, the bit lines for the columns in the multiplexed group of columns 100 are precharged to a memory power supply voltage VDD. A bit line precharge signal BL PRE controls whether a precharge circuit 110 precharges the bit lines for the zeroth column. Similarly, the same bit line precharge signal BL PRE controls whether a precharge circuit 115 precharges the bit lines for the first column. As defined herein, a binary signal is deemed to be asserted when the binary signal is true, regardless of whether the true state is represented by an active-high or an active-low convention. In an active-low convention, a signal is thus asserted by being discharged to ground. Conversely, a signal is asserted by being charged to a power supply voltage in an active-high convention.
As shown in
Referring again to
The asserted write mux signal is denoted as a write mux signal 215 in
Should the write 0 signal be asserted during the write operation, transistor M1 is switched on to discharge the WD node and thus discharge the bit line of the write-selected column. A write 1 signal that is the complement of the write 0 signal controls the gate of the transistor M2. Should the write 0 signal be asserted during the write operation, transistor M2 will thus stay off, isolating the WDB node and the complement bit line of the write-selected column from ground. The assertion of the write 0 signal thus discharges the bit line and maintains the precharge of the complement bit line so as to write a binary zero to the selected bitcell in the write-selected column. Conversely, an assertion of the write 1 signal during the write operation causes the complement bit line to be discharged and maintains the precharge of the bit line so as to write a binary one to the selected bitcell in the write-selected column.
The cleanup operation discussed from time t1 to time t2 to the write-selected column is eliminated in the enhanced serial read write memories disclosed herein. Instead, the cleanup occurs only to the write-unselected columns. In that regard, note how the write-selected bit line voltage 225 was already in a partially-discharged state (partially discharged from the memory power supply voltage) prior to time t1. Should the binary value being written in the write operation also require the write-selected bit line voltage 225 to be discharged to ground, it may readily be appreciated that power consumption is reduced by not performing a cleanup operation only to then have to discharge the write-selected bit line voltage 225 again. Even if the binary value being written is such that the write-selected bit line voltage 225 must be charged to the memory power supply voltage, note that the complement bit line for the write-selected column would then have started to discharge during the read operation. The complement bit line would then be fully discharged during the write operation without an intervening precharge. It will thus be appreciated that one of the bit lines (either the bit line or its complement) for the write-selected column will already be partially discharged from the read operation and then fully discharged during the subsequent write operation without the need for an intervening precharge. The elimination of the cleanup operation to the write-selected column thus saves substantial power.
Although a cleanup operation occurs to the write-unselected column (or write-unselected columns for implementations with the number of multiplexed columns being greater than two), note that the memory speed is still enhanced since this cleanup operation may occur in parallel with the write operation to the write-selected column. In contrast, the write operation for the write-selected column cannot start until the cleanup operation is finished in a traditional memory. Since the cleanup operation takes time, the write operation speed for a traditional serial read write memory is increased by increasing the size of the write driver transistors (e.g., transistors M1 and M2 discussed earlier) and/or by decreasing their threshold voltages. But this increased write operation speed then comes at the cost of increased leakage through the write driver transistors. The enhanced serial read write memories disclosed herein may use relatively smaller write driver transistors so as to reduce leakage and thus reduce power consumption. These relatively-small write driver transistors are adequate due to the time-savings of simultaneously performing the cleanup to the write-unselected column(s) while writing to the write-selected column. Some example enhanced serial read write memories will now be discussed in more detail.
An example multiplexed group of columns 300 for a bank in an enhanced serial read write memory is shown in
Since the cleanup operation occurs only to the write-unselected column (or write-unselected columns in a MUX4 or greater implementation), there is a separate pre-charge signal for each column. For example, a zeroth bit line precharge signal BL PRE<0> controls whether a precharge circuit 310 precharges the bit lines for the zeroth column. Similarly, a first bit line precharge signal BL PRE<1> controls whether a precharge circuit 315 precharges the bit lines for the first column. Both of these precharge signals may be active-low signals. As discussed earlier, a binary signal is deemed to be asserted herein when the binary signal is true, regardless of whether the true state is represented by an active-high or an active-low convention. In an active-low convention, a binary signal is thus asserted by being discharged to ground. Conversely, a binary signal is asserted by being charged to a power supply voltage in an active-high convention.
The bitcells in the multiplexed group of columns 300 are arranged into N rows, where N is a plural positive integer. For illustration clarity, only a zeroth row and an (N−1)th row are shown in
Prior to the read operation beginning at time t0, the bit lines for the columns in the multiplexed group of columns 300 are precharged to a memory power supply voltage VDD. Depending upon which column is the write-selected column, one of the precharge signals may also be denoted as a write-selected bit line precharge signal 420 whereas the precharge signal for the write-unselected column may be denoted as a write-unselected bit line precharge signal 430 as shown in
The read operation may be to either the write-selected column or the write-unselected column. While the word line voltage 410 is asserted during the read operation from time t0 to a time t1, a voltage difference develops across the bit line pairs in each column that intersects with the word line, regardless of whether the column is selected or not. For illustration clarity, just one bit line voltage (a write-selected bit line voltage 425) is shown for the write-selected column. Similarly, just one bit line voltage (a write-unselected bit line voltage 435) is shown for the write-unselected column. In this example, the binary value stored in the accessed bitcell for the write-selected column and stored in the accessed bitcell for the write-unselected column is such that both the write-selected bit line voltage 425 and the write-unselected bit line voltage 435 decline during the read operation. Should the accessed bitcell be storing a complement of this binary value, then the write-selected bit line voltage 425 and the write-unselected bit line voltage 435 would both substantially remain charged to the memory power supply during the read operation. Note that at the conclusion of the read operation at time t1, there is no cleanup operation for the write-selected column. Instead, the write operation begins at time t1 with the assertion of a write mux signal 415. Depending upon which column is the write-selected column, the write mux signal 415 may be one of the write mux 1 or 0 signals discussed earlier.
A cleanup operation for the write-unselected column begins at time t1 with the assertion of the write-unselected bit line precharge signal 430 (recall that the bit line precharge signals in one implementation are active-low such that they are asserted by being discharged). During the cleanup operation, the word line voltage 410 is released. The write-unselected bit line voltage 435 is thus precharged back to the memory power supply voltage during the cleanup operation.
Prior to or approximate with time t2, the word line voltage 410 is again asserted. Although
With regard to the write operation to the write-selected column, note that it may be the case that the binary value being written is such that the write-selected bit line voltage 425 is fully discharged after time t1. It may readily be appreciated that a considerable amount of power was saved by not first cleaning up the write-selected bit line voltage 425 in that scenario since the read operation resulted in the write-selected bit line voltage 425 being partially discharged. Alternatively, it may be the case that the binary value being written is such that the write-selected bit line voltage 425 must be charged to the memory power supply voltage during the read operation. Since there is no assertion of the write-selected bit line precharge voltage 420 between the serial read and write operations, the write driver itself performs this bit line charging.
Referring again to
Suppose that a binary 1 is to be written to the accessed bitcell during the write operation. In that case, the write 1 signal is asserted by being charged to the memory power supply voltage whereas the write 0 signal is de-asserted by being discharged to ground. The discharge of the write 0 signal switches on transistor P1 to cause the bit line in the write-selected column to be charged to the memory power supply voltage. Conversely, the assertion of the write 1 signal switches on transistor M2 to cause the complement bit line in the write-selected column to be discharged to ground. Should a binary 0 instead be written to the accessed bitcell during the write operation, the write 0 signal is asserted by being charged to the memory power supply voltage whereas the write 1 signal is de-asserted by being discharged to ground. The discharge of the write 1 signal switches on transistor P2 to cause the complement bit line in the write-selected column to be charged to the memory power supply voltage. Conversely, the assertion of the write 0 signal switches on transistor M1 to cause the bit line in the write-selected column to be discharged to ground.
Regardless of whether a binary 1 or a binary 0 is to be written during the write operation, note that 50% of the time this binary value will equal the binary value being read during the preceding read operation. In that case, either the bit line or the complement bit line voltage will behave as shown for the write-selected bit line voltage 425: the voltage decline that began during the read operation to a partially-discharged state is then accelerated during the write operation beginning after time t1 so that the partially-discharged state becomes a fully-discharged-to-ground state. It may readily be appreciated that it saves a considerable amount of power to not cleanup such a bit line voltage between the read and write operations. Even if the bit line voltage must be recharged through the write driver as discussed with regard to transistors P1 and P2, note that the write operation speed is increased since the write operation may begin with the assertion of the write mux signal 415 at time t1.
At time t2, the word line voltage 410 is again asserted for the write operation. From time t1 to just prior to a time t3, the write mux signal 415 and the word line voltage 410 continue to be asserted to provide a sufficient write margin to the write operation. At time t3, the word line voltage 410, the write mux signal 415, and the write-unselected bit line precharge signal 430 are all released. Time t3 is also the end of the clock cycle for the memory clock signal 415. The write-selected bit line precharge voltage 420 remains released from time t0 to just before time t3. As compared to the traditional memory, the enhanced serial read write memory results in a shorter memory clock cycle and thus a faster serial read write cycle because of the write operation to the write-selected column beginning in parallel with the cleanup to the write-unselected column at time t1.
An enhanced serial read write memory 500 with a first bank (Bank 1) and a second bank (Bank 2) of bitcells is shown in
It may thus be the case that a read operation occurs to a multiplexed column group in a bank during a memory clock cycle but the write operation in the memory clock cycle is not directed to the same multiplexed group of columns and bank. Referring again to
The enhanced serial read write memories disclosed herein may be pseudo-dual-port static-random-access memories. An example six-transistor bitcell 600 for an example pseudo-dual-port static-random-access memory (SRAM) is shown in
An example method of operation for an enhanced serial read write memory will now be discussed with reference to the flowchart of
An enhanced serial read write memory may as disclosed herein may be incorporated in a wide variety of electronic systems. For example, as shown in
Some example implementations are described by the following numbered clauses:
As those of some skill in this art will by now appreciate and depending on the particular application at hand, many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof as defined by the appended claims. In light of this, the scope of the present disclosure should not be limited to that of the particular implementations illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.
