Pradeep Yelehanka

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Wafer level encapsulation for MEMS device
- Patent number 10,793,421
- Issue date Oct 6, 2020
- VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.
- Natarajan Rajasekaran
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Wafer level packaging for MEMS device
- Patent number 10,301,171
- Issue date May 28, 2019
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Siddharth Chakravarty
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Semiconductor devices with cavities and methods for fabricating sem...
- Patent number 9,932,224
- Issue date Apr 3, 2018
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Siddharth Chakravarty
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Integrated circuits with alignment marks and methods of producing t...
- Patent number 9,633,882
- Issue date Apr 25, 2017
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Ying Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating semiconductor or micromachined devices with...
- Patent number 9,620,373
- Issue date Apr 11, 2017
- GLOBALFOUNDRIES SINGAPOREPTE. LTD.
- Siddharth Chakravarty
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding method using porosified surfaces for making stacked structures
- Patent number 9,272,899
- Issue date Mar 1, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Rama Krishna Kotlanka
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Bonding method using porosified surfaces for making stacked structures
- Patent number 8,940,616
- Issue date Jan 27, 2015
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Rama Krishna Kotlanka
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Integrated circuit system with through silicon via and method of ma...
- Patent number 8,536,705
- Issue date Sep 17, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Pradeep Ramachandramurthy Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package interconnects
- Patent number 8,513,767
- Issue date Aug 20, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Rama Krishna Kotlanka
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Processing with reduced line end shortening ratio
- Patent number 8,394,724
- Issue date Mar 12, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Hai Cong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor local interconnect and contact
- Patent number 8,304,834
- Issue date Nov 6, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Pradeep Ramachandramurthy Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Critical dimension for trench and vias
- Patent number 8,293,545
- Issue date Oct 23, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Hai Cong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system including nitride layer technology
- Patent number 8,283,263
- Issue date Oct 9, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Sripad Sheshagiri Nagarad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system with through silicon via and method of ma...
- Patent number 8,236,688
- Issue date Aug 7, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Pradeep Ramachandramurthy Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory manufacturing method using STI trench implantation
- Patent number 8,236,646
- Issue date Aug 7, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Tze Ho Simon Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system employing stress memorization transfer
- Patent number 7,964,894
- Issue date Jun 21, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Elgin Kiok Boone Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacture an integrated circuit system with through sil...
- Patent number 7,960,282
- Issue date Jun 14, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Pradeep Ramachandramurthy Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin film etching method and semiconductor device fabrication using...
- Patent number 7,879,732
- Issue date Feb 1, 2011
- Chartered Semiconductor Manufacturing Ltd.
- Xiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system employing stress memorization transfer
- Patent number 7,759,207
- Issue date Jul 20, 2010
- Chartered Semiconductor Manufacturing Ltd.
- Elgin Kiok Boone Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with protected implantation profiles and method...
- Patent number 7,501,683
- Issue date Mar 10, 2009
- Chartered Semiconductor Manufacturing Ltd.
- Tommy Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOSFET device with low gate contact resistance
- Patent number 7,382,027
- Issue date Jun 3, 2008
- Chartered Semiconductor Manufacturing, Ltd.
- Purakh Raj Verma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form both high and low-k materials over the same dielectr...
- Patent number 7,323,736
- Issue date Jan 29, 2008
- Chartered Semiconductor Manufacturing Ltd.
- Pradeep Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thyristor-based SRAM
- Patent number 7,285,804
- Issue date Oct 23, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Elgin Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Horizontal tram
- Patent number 7,183,590
- Issue date Feb 27, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Jia Zhen Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thyristor-based SRAM
- Patent number 7,148,522
- Issue date Dec 12, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Elgin Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor local interconnect and contact
- Patent number 7,119,005
- Issue date Oct 10, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Pradeep Ramachandramurthy Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Horizontal TRAM and method for the fabrication thereof
- Patent number 7,081,378
- Issue date Jul 25, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Jia Zhen Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with protected implantation profiles and method...
- Patent number 7,067,362
- Issue date Jun 27, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Tommy Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form both high and low-k materials over the same dielectr...
- Patent number 7,060,193
- Issue date Jun 13, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Pradeep Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-level gate SONOS flash memory device with high voltage oxide...
- Patent number 7,015,101
- Issue date Mar 21, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Jia Zhen Zheng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
WAFER LEVEL PACKAGING FOR MEMS DEVICE
- Publication number 20190144265
- Publication date May 16, 2019
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Siddharth CHAKRAVARTY
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
WAFER LEVEL ENCAPSULATION FOR MEMS DEVICE
- Publication number 20190144269
- Publication date May 16, 2019
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Natarajan RAJASEKARAN
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
SEMICONDUCTOR DEVICES WITH CAVITIES AND METHODS FOR FABRICATING SEM...
- Publication number 20180170748
- Publication date Jun 21, 2018
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Siddharth Chakravarty
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
SEMICONDUCTOR DEVICES WITH CAVITIES AND METHODS FOR FABRICATING SEM...
- Publication number 20170174507
- Publication date Jun 22, 2017
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Siddharth Chakravarty
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
INTEGRATED CIRCUITS WITH ALIGNMENT MARKS AND METHODS OF PRODUCING T...
- Publication number 20170092523
- Publication date Mar 30, 2017
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Ying Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDING METHOD USING POROSIFIED SURFACES FOR MAKING STACKED STRUCTURES
- Publication number 20150115453
- Publication date Apr 30, 2015
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Rama Krishna KOTLANKA
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
CMOS COMPATIBLE WAFER BONDING LAYER AND PROCESS
- Publication number 20150048509
- Publication date Feb 19, 2015
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Ranganathan NAGARAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDING METHOD USING POROSIFIED SURFACES FOR MAKING STACKED STRUCTURES
- Publication number 20140030847
- Publication date Jan 30, 2014
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Rama Krishna KOTLANKA
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY
- Publication number 20130034954
- Publication date Feb 7, 2013
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Sripad Sheshagiri Nagarad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE INTERCONNECTS
- Publication number 20120241901
- Publication date Sep 27, 2012
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Rama Krishna KOTLANKA
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MA...
- Publication number 20120205806
- Publication date Aug 16, 2012
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Pradeep Ramachandramurthy Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MA...
- Publication number 20110237072
- Publication date Sep 29, 2011
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Pradeep Ramachandramurthy Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MA...
- Publication number 20100297844
- Publication date Nov 25, 2010
- Chartered Semiconductor Manufacturing LTD.
- Pradeep Ramachandramurthy Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS MEMORIZATION TRANSFER
- Publication number 20100230765
- Publication date Sep 16, 2010
- Chartered Semiconductor Manufacturing LTD.
- Elgin Kiok Boone Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN FILM ETCHING METHOD AND SEMICONDUCTOR DEVICE FABRICATION USING...
- Publication number 20090156010
- Publication date Jun 18, 2009
- Xiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CRITICAL DIMENSION FOR TRENCH AND VIAS
- Publication number 20090108257
- Publication date Apr 30, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Hai Cong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS MEMORIZATION TRANSFER
- Publication number 20080230841
- Publication date Sep 25, 2008
- Chartered Semiconductor Manufacturing LTD.
- Elgin Kiok Boone Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Processing with Reduced Line End Shortening Ratio
- Publication number 20080054477
- Publication date Mar 6, 2008
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Hai CONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY
- Publication number 20080032513
- Publication date Feb 7, 2008
- Chartered Semiconductor Manufacturing LTD.
- Sripad Sheshagiri Nagarad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR LOCAL INTERCONNECT AND CONTACT
- Publication number 20060281253
- Publication date Dec 14, 2006
- Chartered Semiconductor Manufacturing LTD.
- Pradeep Ramachandramurthy Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH PROTECTED IMPLANTATION PROFILES AND METHOD...
- Publication number 20060220110
- Publication date Oct 5, 2006
- Chartered Semiconductor Manufacturing LTD.
- Tommy Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HORIZONTAL TRAM
- Publication number 20060214185
- Publication date Sep 28, 2006
- Chartered Semiconductor Manufacturing LTD.
- Jia Zhen Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thyristor-based SRAM
- Publication number 20050167664
- Publication date Aug 4, 2005
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Elgin Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of making direct contact on gate by using dielectric stop layer
- Publication number 20050136573
- Publication date Jun 23, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Purakh Rajverma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming an inductor with continuous metal deposition
- Publication number 20050124131
- Publication date Jun 9, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Chit Hweing
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-volatile memory and manufacturing method using STI trench impla...
- Publication number 20050101102
- Publication date May 12, 2005
- Chartered Semiconductor Manufacturing LTD.
- Tze Ho Simon Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with protected implantation profiles and method...
- Publication number 20050085056
- Publication date Apr 21, 2005
- Chartered Semiconductor Manufacturing LTD.
- Tommy Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THYRISTOR-BASED SRAM AND METHOD FOR THE FABRICATION THEREOF
- Publication number 20050026337
- Publication date Feb 3, 2005
- Chartered Semiconductor Manufacturing LTD.
- Elgin Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thyistor-based SRAM and method using quasi-planar finfet process fo...
- Publication number 20050026343
- Publication date Feb 3, 2005
- Chartered Semiconductor Manufacturing LTD.
- Elgin Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming an inductor with continuous metal deposition
- Publication number 20040217440
- Publication date Nov 4, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Chit Hwei Ng
- H01 - BASIC ELECTRIC ELEMENTS

Pradeep Yelehanka

Person

Patents Grantslast 30 patents

Wafer level encapsulation for MEMS device

Wafer level packaging for MEMS device

Semiconductor devices with cavities and methods for fabricating sem...

Integrated circuits with alignment marks and methods of producing t...

Methods for fabricating semiconductor or micromachined devices with...

Bonding method using porosified surfaces for making stacked structures

Bonding method using porosified surfaces for making stacked structures

Integrated circuit system with through silicon via and method of ma...

Package interconnects

Processing with reduced line end shortening ratio

Semiconductor local interconnect and contact

Critical dimension for trench and vias

Integrated circuit system including nitride layer technology

Integrated circuit system with through silicon via and method of ma...

Non-volatile memory manufacturing method using STI trench implantation

Integrated circuit system employing stress memorization transfer

Method of manufacture an integrated circuit system with through sil...

Thin film etching method and semiconductor device fabrication using...

Integrated circuit system employing stress memorization transfer

Integrated circuit with protected implantation profiles and method...

MOSFET device with low gate contact resistance

Method to form both high and low-k materials over the same dielectr...

Thyristor-based SRAM

Horizontal tram

Thyristor-based SRAM

Semiconductor local interconnect and contact

Horizontal TRAM and method for the fabrication thereof

Integrated circuit with protected implantation profiles and method...

Method to form both high and low-k materials over the same dielectr...

Multi-level gate SONOS flash memory device with high voltage oxide...

Patents Applicationslast 30 patents

WAFER LEVEL PACKAGING FOR MEMS DEVICE

WAFER LEVEL ENCAPSULATION FOR MEMS DEVICE

SEMICONDUCTOR DEVICES WITH CAVITIES AND METHODS FOR FABRICATING SEM...

SEMICONDUCTOR DEVICES WITH CAVITIES AND METHODS FOR FABRICATING SEM...

INTEGRATED CIRCUITS WITH ALIGNMENT MARKS AND METHODS OF PRODUCING T...

BONDING METHOD USING POROSIFIED SURFACES FOR MAKING STACKED STRUCTURES

CMOS COMPATIBLE WAFER BONDING LAYER AND PROCESS

BONDING METHOD USING POROSIFIED SURFACES FOR MAKING STACKED STRUCTURES

INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY

PACKAGE INTERCONNECTS

INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MA...

INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MA...

INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MA...

INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS MEMORIZATION TRANSFER

THIN FILM ETCHING METHOD AND SEMICONDUCTOR DEVICE FABRICATION USING...

CRITICAL DIMENSION FOR TRENCH AND VIAS

INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS MEMORIZATION TRANSFER

Processing with Reduced Line End Shortening Ratio

INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY

SEMICONDUCTOR LOCAL INTERCONNECT AND CONTACT

INTEGRATED CIRCUIT WITH PROTECTED IMPLANTATION PROFILES AND METHOD...

HORIZONTAL TRAM

Thyristor-based SRAM

Method of making direct contact on gate by using dielectric stop layer

Method of forming an inductor with continuous metal deposition

Non-volatile memory and manufacturing method using STI trench impla...

Integrated circuit with protected implantation profiles and method...

THYRISTOR-BASED SRAM AND METHOD FOR THE FABRICATION THEREOF

Thyistor-based SRAM and method using quasi-planar finfet process fo...

Method of forming an inductor with continuous metal deposition