Patent Application
20080054477
a-b, respectively, show SEM images of gate conductors patterned in accordance with one embodiment of the invention and by conventional processes using a hard mask.
The present invention relates to semiconductor processing. More particularly, the present invention provides a process for forming patterned line features with reduced line end shortening. In one embodiment, the line feature comprises polysilicon lines which serve, for example, as gate conductors. Forming other types of line features is also contemplated and within the scope of the invention, particularly where low LES ratio is desirable.
In accordance with one embodiment of the invention, forming a line feature with sub-ground rule dimensions can be achieved as part of the etch that forms the line feature. The etch can include an initial etch with appropriate etch chemistry which substantially produces the feature based on a patterned resist mask and an over-etch to complete the patterning of the feature, wherein the initial etch uses an appropriate etch chemistry to trim the line feature to desired dimensions. By trimming the line feature as part of the etch that forms the line feature, LES is substantially reduced.
In one embodiment, the patterned resist layer is partially trimmed at step 310. The partial resist trim reduces the CD to sub-ground rule dimensions, but insufficiently to satisfy the desired CD of the line feature. The partial trim should result in LES ratio of less than 1.5, preferably less than 1.4, more preferably less than 1.3 and even more preferably, from about 1.1-1.2. The partial trim, for example, trims up to about 40% of the GD, preferably about 10-40% of the GD and more preferably about 20-30% of the GD. In one embodiment, the partial trim trims less than about 10 nm of the resist. The amount of resist trimming can be adjusted to accommodate different processes, so as to facilitate achieving the desired CD with low LES ratio. The partial resist trim can be performed using conventional O2-based chemistry.
At step 320, exposed portions of the BARC layer unprotected by the resist layer are removed to expose portions of the layer beneath the BARC layer. The layer beneath the mask, in some applications, can include more than one layer. The layer stack at step 330 is patterned based on the resist mask to form a line feature. In accordance with one embodiment of the invention, the etch forms a line feature with the desired sub-ground rule CD. Unlike in resist trim processes, resist “foots” are not removed during the etch, thus reducing LES ratio. The etch comprises, in one embodiment, plasma etching. The etch employs appropriate chemistry for etching in the vertical direction with some etching in the horizontal direction. The desired ratio of vertical to horizontal etching (VE:HE) will depend on the height of the feature and the value of GD. The etch chemistry can be tailored to achieve the desired VE:HE ratio.
In one embodiment, the layer stack comprises layers for forming gate conductors. The gate conductor, for example, comprises a polysilicon layer over a gate dielectric layer. The gate dielectric layer comprises, for example, an oxide layer. Other types of line features are also useful. It is understood that the gate conductor need not be straight. The gate conductor can be S-shaped, L-shaped or other shapes. In one embodiment, a non-chlorine-based chemistry is used to etch the polysilicon layer. Using a non-chlorine based chemistry can reduce isotropic etching of the polysilicon sidewalls, minimizing profile bowing.
In one embodiment, the etch chemistry used to etch the polysilicon layer comprises first and second fluorine-based chemistries. The first chemistry comprises a high fluorine content while the second chemistry comprises a low fluorine/carbon ratio or high carbon content. The first chemistry etches the polysilicon layer while the second chemistry serves to passivate the polysilicon sidewalls to prevent bowing, maintaining the profile of the gate conductor. The first chemistry can comprise SF6, C2F6 or CF4 and the second chemistry can comprise CH2F2 or C4F8. Preferably, the first and second chemistries respectively comprise SF6 and CH2F2. Alternatively, the first and second chemistries respectively comprise SF6 and C4F8. The molar ratio of the first and second chemistries is about 1:1 to 1:3. Other types of fluorine-based or non-fluorine based chemistries may also be useful. The etch can be performed with low bias power and relatively high source power. Under these conditions, a high density, low bombardment energy plasma is formed such that a high etch rate can be achieved while minimizing the degree of plasma damage to the gate dielectric layer.
In one embodiment, the etch to form the line feature with the desired sub-ground rule CD stops with a soft landing at step 340. The soft landing step, for example, is highly selective to the gate dielectric material to reduce or eliminate pitting of the gate dielectric layer. After the soft landing step, an over-etch is performed at step 350. The over-etch, for example, has an even higher selectivity to the gate dielectric material to prevent damage to the gate dielectric layer.
a shows a SEM image of gate conductors patterned in accordance with one embodiment of the invention, and
As described, LES can be reduced by trimming the layer stack to achieve the desired CD during the etch to form the line feature. Furthermore, CD through pitch performance is improved because any microloading effect is counteracted by a greater reduction in line CD in isolated regions. Additionally, the present process is compatible with current STI/silicon nitride (SiN) liner schemes. It is thus readily integrated into existing processes with minimal expense in terms of both resources and developmental time. Finally, as compared with conventional hard mask processes, lower long-term production costs can be achieved.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. Scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.
| Number | Date | Country | |
|---|---|---|---|
| 60824078 | Aug 2006 | US |
