Prakhar SRIVASTAVA

Person

Lucknow, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Memory devices write buffer management
- Patent number 12,197,775
- Issue date Jan 14, 2025
- QUALCOMM Incorporated
- Santhosh Reddy Akavaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for reducing latencies associated with link s...
- Patent number 12,174,757
- Issue date Dec 24, 2024
- QUALCOMM Incorporated
- Santhosh Reddy Akavaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to reduce exit latency for deeper power saving modes L2 i...
- Patent number 12,164,448
- Issue date Dec 10, 2024
- QUALCOMM Incorporated
- Ravindranath Doddi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data rate increase for faulty lane recovery in multiple lane data l...
- Patent number 12,153,527
- Issue date Nov 26, 2024
- QUALCOMM Incorporated
- Santhosh Reddy Akavaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management for peripheral component interconnect
- Patent number 12,079,061
- Issue date Sep 3, 2024
- QUALCOMM Incorporated
- Prakhar Srivastava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write buffer and logical unit management in a data storage device
- Patent number 12,056,364
- Issue date Aug 6, 2024
- QUALCOMM Incorporated
- Yogananda Rao Chillariga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency reduction for link speed switching in multiple lane data links
- Patent number 12,019,577
- Issue date Jun 25, 2024
- QUALCOMM Incorporated
- Prakhar Srivastava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management for peripheral component interconnect
- Patent number 11,934,335
- Issue date Mar 19, 2024
- QUALCOMM Incorporated
- Prakhar Srivastava
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR UPDATING MEMORY TABLES
- Publication number 20250021478
- Publication date Jan 16, 2025
- QUALCOMM Incorporated
- Manish GARG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERRUPTING MEMORY ACCESS DURING BACKGROUND OPERATIONS ON A MEMORY...
- Publication number 20250013572
- Publication date Jan 9, 2025
- QUALCOMM Incorporated
- Sonali JABREVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR REDUCING LATENCIES ASSOCIATED WITH LINK S...
- Publication number 20240427709
- Publication date Dec 26, 2024
- QUALCOMM Incorporated
- Santhosh Reddy AKAVARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism To Enhance PCIe Generation Switching
- Publication number 20240427710
- Publication date Dec 26, 2024
- QUALCOMM Incorporated
- Santhosh Reddy AKAVARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Universal Flash Storage Shared Write Booster Buffer Enhancements
- Publication number 20240411481
- Publication date Dec 12, 2024
- QUALCOMM Incorporated
- Chintalapati BHARATH SAI VARMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUEUED CURRENT LEVEL ADJUSTMENT IN A FLASH MEMORY SYSTEM
- Publication number 20240411463
- Publication date Dec 12, 2024
- QUALCOMM Incorporated
- Chintalapati Bharath Sai Varma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARE MEMORY MANAGEMENT IN DATA STORAGE DEVICE
- Publication number 20240402923
- Publication date Dec 5, 2024
- QUALCOMM Incorporated
- Santhosh Reddy AKAVARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGICAL TO PHYSICAL LOOKUP TABLE UPDATE IN A FLASH MEMORY SYSTEM
- Publication number 20240370378
- Publication date Nov 7, 2024
- QUALCOMM Incorporated
- Santhosh Reddy Akavaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES WRITE BUFFER MANAGEMENT
- Publication number 20240319913
- Publication date Sep 26, 2024
- QUALCOMM Incorporated
- Santhosh Reddy AKAVARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHANNEL DIRECTION MANAGEMENT FOR BUS INTERFACES
- Publication number 20240264965
- Publication date Aug 8, 2024
- QUALCOMM Incorporated
- Prakhar Srivastava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA RATE INCREASE FOR FAULTY LANE RECOVERY IN MULTIPLE LANE DATA L...
- Publication number 20240202140
- Publication date Jun 20, 2024
- QUALCOMM Incorporated
- Santhosh Reddy AKAVARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLOW CONTROL BETWEEN PERIPHERAL COMPONENT INTERCONNECT EXPRESS DEVICES
- Publication number 20240143434
- Publication date May 2, 2024
- QUALCOMM Incorporated
- Santhosh Reddy AKAVARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LATENCY REDUCTION FOR LINK SPEED SWITCHING IN MULTIPLE LANE DATA LINKS
- Publication number 20240111700
- Publication date Apr 4, 2024
- QUALCOMM Incorporated
- Prakhar SRIVASTAVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGEMENT FOR PERIPHERAL COMPONENT INTERCONNECT
- Publication number 20240111354
- Publication date Apr 4, 2024
- QUALCOMM Incorporated
- Prakhar SRIVASTAVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGEMENT FOR PERIPHERAL COMPONENT INTERCONNECT
- Publication number 20230325342
- Publication date Oct 12, 2023
- QUALCOMM Incorporated
- Prakhar SRIVASTAVA
- G06 - COMPUTING CALCULATING COUNTING

Prakhar SRIVASTAVA

Person

Patents Grantslast 30 patents

Memory devices write buffer management

Apparatus and methods for reducing latencies associated with link s...

Mechanism to reduce exit latency for deeper power saving modes L2 i...

Data rate increase for faulty lane recovery in multiple lane data l...

Power management for peripheral component interconnect

Write buffer and logical unit management in a data storage device

Latency reduction for link speed switching in multiple lane data links

Power management for peripheral component interconnect

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR UPDATING MEMORY TABLES

INTERRUPTING MEMORY ACCESS DURING BACKGROUND OPERATIONS ON A MEMORY...

APPARATUS AND METHODS FOR REDUCING LATENCIES ASSOCIATED WITH LINK S...

Mechanism To Enhance PCIe Generation Switching

Universal Flash Storage Shared Write Booster Buffer Enhancements

QUEUED CURRENT LEVEL ADJUSTMENT IN A FLASH MEMORY SYSTEM

SPARE MEMORY MANAGEMENT IN DATA STORAGE DEVICE

LOGICAL TO PHYSICAL LOOKUP TABLE UPDATE IN A FLASH MEMORY SYSTEM

MEMORY DEVICES WRITE BUFFER MANAGEMENT

CHANNEL DIRECTION MANAGEMENT FOR BUS INTERFACES

DATA RATE INCREASE FOR FAULTY LANE RECOVERY IN MULTIPLE LANE DATA L...

FLOW CONTROL BETWEEN PERIPHERAL COMPONENT INTERCONNECT EXPRESS DEVICES

LATENCY REDUCTION FOR LINK SPEED SWITCHING IN MULTIPLE LANE DATA LINKS

POWER MANAGEMENT FOR PERIPHERAL COMPONENT INTERCONNECT

POWER MANAGEMENT FOR PERIPHERAL COMPONENT INTERCONNECT