Prasanna Khare

Person

Schenectady, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method to co-integrate SiGe and Si channels for finFET devices
- Patent number 11,670,554
- Issue date Jun 6, 2023
- Bell Semiconductor, LLC
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-fin FINFET device including epitaxial growth barrier on outsi...
- Patent number 11,610,886
- Issue date Mar 21, 2023
- Bell Semiconductor, LLC
- Qing Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-fin FINFET device including epitaxial growth barrier on outsi...
- Patent number 11,069,682
- Issue date Jul 20, 2021
- STMicroelectronics, Inc.
- Qing Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-fin FINFET device including epitaxial growth barrier on outsi...
- Patent number 10,580,771
- Issue date Mar 3, 2020
- STMicroelectronics, Inc.
- Qing Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to co-integrate SiGe and Si channels for finFET devices
- Patent number 10,340,195
- Issue date Jul 2, 2019
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully substrate-isolated FinFET transistor
- Patent number 10,170,546
- Issue date Jan 1, 2019
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-on-nothing transistor semiconductor structure with channel...
- Patent number 10,170,475
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Stephane Allegret-Maret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Facet-free strained silicon transistor
- Patent number 10,134,895
- Issue date Nov 20, 2018
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Facet-free strained silicon transistor
- Patent number 10,134,899
- Issue date Nov 20, 2018
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-fin FINFET device including epitaxial growth barrier on outsi...
- Patent number 10,062,690
- Issue date Aug 28, 2018
- STMicroelectronics, Inc.
- Qing Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-on-nothing transistor semiconductor structure with channel...
- Patent number 10,038,075
- Issue date Jul 31, 2018
- International Business Machines Corporation
- Stephane Allegret-Maret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a semiconductor device using a dummy gate
- Patent number 9,991,351
- Issue date Jun 5, 2018
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a semiconductor device using a dummy gate
- Patent number 9,905,662
- Issue date Feb 27, 2018
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully substrate-isolated FinFET transistor
- Patent number 9,893,147
- Issue date Feb 13, 2018
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to co-integrate SiGe and Si channels for finFET devices
- Patent number 9,847,260
- Issue date Dec 19, 2017
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin field effect transistor device with reduced overlap capacitance...
- Patent number 9,793,378
- Issue date Oct 17, 2017
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation regions for SOI devices
- Patent number 9,768,055
- Issue date Sep 19, 2017
- STMicroelectronics, Inc.
- Qing Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to co-integrate SiGe and Si channels for finFET devices
- Patent number 9,685,380
- Issue date Jun 20, 2017
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin isolation structures facilitating different fin isolation schemes
- Patent number 9,673,222
- Issue date Jun 6, 2017
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-on-nothing transistor semiconductor structure with channel...
- Patent number 9,620,506
- Issue date Apr 11, 2017
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-on-nothing transistor semiconductor structure with channel...
- Patent number 9,620,507
- Issue date Apr 11, 2017
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully substrate-isolated FinFET transistor
- Patent number 9,520,393
- Issue date Dec 13, 2016
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual shallow trench isolation liner for preventing electrical shorts
- Patent number 9,502,292
- Issue date Nov 22, 2016
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for the formation of fin structures for FinFET devices
- Patent number 9,437,504
- Issue date Sep 6, 2016
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-fin FINFET device including epitaxial growth barrier on outsi...
- Patent number 9,419,111
- Issue date Aug 16, 2016
- STMicroelectronics, Inc.
- Qing Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin transformation process and isolation structures facilitating di...
- Patent number 9,349,730
- Issue date May 24, 2016
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual shallow trench isolation liner for preventing electrical shorts
- Patent number 9,252,052
- Issue date Feb 2, 2016
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual shallow trench isolation liner for preventing electrical shorts
- Patent number 9,171,757
- Issue date Oct 27, 2015
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bulk finFET semiconductor-on-nothing integration
- Patent number 9,166,023
- Issue date Oct 20, 2015
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor having a stressed body
- Patent number 9,123,809
- Issue date Sep 1, 2015
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
- Publication number 20230260846
- Publication date Aug 17, 2023
- Bell Semiconductor, LLC
- Nicolas LOUBET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSI...
- Publication number 20230197720
- Publication date Jun 22, 2023
- Bell Semiconductor, LLC
- Qing LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
- Publication number 20230121119
- Publication date Apr 20, 2023
- Bell Semiconductor, LLC
- Nicolas LOUBET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSI...
- Publication number 20210327874
- Publication date Oct 21, 2021
- STMicroelectronics, Inc.
- QING LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSI...
- Publication number 20200161299
- Publication date May 21, 2020
- STMicroelectronics, Inc.
- QING LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
- Publication number 20190279912
- Publication date Sep 12, 2019
- STMICROELECTRONIS, INC.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSI...
- Publication number 20180350808
- Publication date Dec 6, 2018
- STMicroelectronics, Inc.
- QING LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
- Publication number 20180261674
- Publication date Sep 13, 2018
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR
- Publication number 20180145133
- Publication date May 24, 2018
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
- Publication number 20180068902
- Publication date Mar 8, 2018
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL...
- Publication number 20170179137
- Publication date Jun 22, 2017
- International Business Machines Corporation
- Stephane Allegret-Maret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL...
- Publication number 20170170299
- Publication date Jun 15, 2017
- International Business Machines Corporation
- Stephane Allegret-Maret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR
- Publication number 20170053981
- Publication date Feb 23, 2017
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
- Publication number 20170040427
- Publication date Feb 9, 2017
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSI...
- Publication number 20160322356
- Publication date Nov 3, 2016
- STMicroelectronics, Inc.
- QING LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN ISOLATION STRUCTURES FACILITATING DIFFERENT FIN ISOLATION SCHEMES
- Publication number 20160260742
- Publication date Sep 8, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil JACOB
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FACET-FREE STRAINED SILICON TRANSISTOR
- Publication number 20160149038
- Publication date May 26, 2016
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
- Publication number 20160111338
- Publication date Apr 21, 2016
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
- Publication number 20160104772
- Publication date Apr 14, 2016
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS
- Publication number 20160013096
- Publication date Jan 14, 2016
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES
- Publication number 20150325487
- Publication date Nov 12, 2015
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSI...
- Publication number 20150303285
- Publication date Oct 22, 2015
- STMicroelectronics, Inc.
- Qing Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR THE FORMATION OF DIELECTRIC ISOLATED FIN STRUCTURES FOR...
- Publication number 20150162248
- Publication date Jun 11, 2015
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR
- Publication number 20150108585
- Publication date Apr 23, 2015
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR THE FORMATION OF CMOS TRANSISTORS
- Publication number 20150093861
- Publication date Apr 2, 2015
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BULK FINFET SEMICONDUCTOR-ON-NOTHING INTEGRATION
- Publication number 20150041898
- Publication date Feb 12, 2015
- GLOBALFOUNDRIES INC.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN TRANSFORMATION PROCESS AND ISOLATION STRUCTURES FACILITATING DI...
- Publication number 20150021690
- Publication date Jan 22, 2015
- International Business Machines Corporation
- Ajey Poovannummoottil JACOB
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR FACILTIATING FIN ISOLATION SCHEMES
- Publication number 20150024572
- Publication date Jan 22, 2015
- International Business Machies Corporation
- Ajey P. JACOB
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR HAVING A STRESSED BODY
- Publication number 20150008521
- Publication date Jan 8, 2015
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
- Publication number 20140353716
- Publication date Dec 4, 2014
- NICOLAS LOUBET
- H01 - BASIC ELECTRIC ELEMENTS

Prasanna Khare

Person

Patents Grantslast 30 patents

Method to co-integrate SiGe and Si channels for finFET devices

Multi-fin FINFET device including epitaxial growth barrier on outsi...

Multi-fin FINFET device including epitaxial growth barrier on outsi...

Multi-fin FINFET device including epitaxial growth barrier on outsi...

Method to co-integrate SiGe and Si channels for finFET devices

Fully substrate-isolated FinFET transistor

Silicon-on-nothing transistor semiconductor structure with channel...

Facet-free strained silicon transistor

Facet-free strained silicon transistor

Multi-fin FINFET device including epitaxial growth barrier on outsi...

Silicon-on-nothing transistor semiconductor structure with channel...

Method of making a semiconductor device using a dummy gate

Method of making a semiconductor device using a dummy gate

Fully substrate-isolated FinFET transistor

Method to co-integrate SiGe and Si channels for finFET devices

Fin field effect transistor device with reduced overlap capacitance...

Isolation regions for SOI devices

Method to co-integrate SiGe and Si channels for finFET devices

Fin isolation structures facilitating different fin isolation schemes

Silicon-on-nothing transistor semiconductor structure with channel...

Silicon-on-nothing transistor semiconductor structure with channel...

Fully substrate-isolated FinFET transistor

Dual shallow trench isolation liner for preventing electrical shorts

Method for the formation of fin structures for FinFET devices

Multi-fin FINFET device including epitaxial growth barrier on outsi...

Fin transformation process and isolation structures facilitating di...

Dual shallow trench isolation liner for preventing electrical shorts

Dual shallow trench isolation liner for preventing electrical shorts

Bulk finFET semiconductor-on-nothing integration

Transistor having a stressed body

Patents Applicationslast 30 patents

METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES

MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSI...

METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE

MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSI...

MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSI...

METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES

MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSI...

METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE

FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR

METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES

SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL...

SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL...

FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR

METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE

MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSI...

FIN ISOLATION STRUCTURES FACILITATING DIFFERENT FIN ISOLATION SCHEMES

FACET-FREE STRAINED SILICON TRANSISTOR

METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES

METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE

DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS

METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES

MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSI...

METHOD FOR THE FORMATION OF DIELECTRIC ISOLATED FIN STRUCTURES FOR...

FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR

METHOD FOR THE FORMATION OF CMOS TRANSISTORS

BULK FINFET SEMICONDUCTOR-ON-NOTHING INTEGRATION

FIN TRANSFORMATION PROCESS AND ISOLATION STRUCTURES FACILITATING DI...

PROCESS FOR FACILTIATING FIN ISOLATION SCHEMES

TRANSISTOR HAVING A STRESSED BODY

METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE