Prasanna Srinivasan

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Resistance reduction for word lines in memory arrays
- Patent number 11,587,874
- Issue date Feb 21, 2023
- Intel Corporation
- Sung-Taeg Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatuses having memory cells including a monolithic...
- Patent number 10,879,259
- Issue date Dec 29, 2020
- Micron Technology, Inc.
- Jie Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capping poly channel pillars in stacked circuits
- Patent number 10,319,678
- Issue date Jun 11, 2019
- Intel Corporation
- Hongqi Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatuses having memory cells including a monolithic...
- Patent number 10,090,317
- Issue date Oct 2, 2018
- Micron Technology, Inc.
- Jie Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatuses having memory cells including a monolithic...
- Patent number 9,431,410
- Issue date Aug 30, 2016
- Micron Technology, Inc.
- Jie Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capping poly channel pillars in stacked circuits
- Patent number 9,263,459
- Issue date Feb 16, 2016
- Intel Corporation
- Hongqi Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lithography methods, methods for forming patterning tools and patte...
- Patent number 9,176,385
- Issue date Nov 3, 2015
- Micron Technology, Inc.
- Jianming Zhou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Lithography methods, methods for forming patterning tools and patte...
- Patent number 8,609,302
- Issue date Dec 17, 2013
- Micron Technology, Inc.
- Jianming Zhou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
LOW-COST MASK PUNCH FLOW
- Publication number 20230354611
- Publication date Nov 2, 2023
- Xin FU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLASH MEMORY CHIP WITH SELF ALIGNED ISOLATION FILL BETWEEN PILLARS
- Publication number 20230136139
- Publication date May 4, 2023
- Intel NDTM US LLC
- Anil CHANDOLU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RESISTANCE REDUCTION FOR WORD LINES IN MEMORY ARRAYS
- Publication number 20210265278
- Publication date Aug 26, 2021
- Intel Corporation
- Sung-Taeg Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC...
- Publication number 20190131315
- Publication date May 2, 2019
- Micron Technology, Inc.
- Jie Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC...
- Publication number 20160336341
- Publication date Nov 17, 2016
- Micron Technology, Inc.
- Jie Sun
- G11 - INFORMATION STORAGE
Information Patent Application
CAPPING POLY CHANNEL PILLARS IN STACKED CIRCUITS
- Publication number 20160247756
- Publication date Aug 25, 2016
- Intel Corporation
- Hongqi Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC...
- Publication number 20150123189
- Publication date May 7, 2015
- Micron Technology, Inc.
- Jie Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LITHOGRAPHY METHODS, METHODS FOR FORMING PATTERNING TOOLS AND PATTE...
- Publication number 20140106280
- Publication date Apr 17, 2014
- Micron Technology, Inc.
- Jianming Zhou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
LITHOGRAPHY METHODS, METHODS FOR FORMING PATTERNING TOOLS AND PATTE...
- Publication number 20130052566
- Publication date Feb 28, 2013
- Micron Technology, Inc.
- Jianming Zhou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Prasanna Srinivasan

Person

Patents Grantslast 30 patents

Resistance reduction for word lines in memory arrays

Methods and apparatuses having memory cells including a monolithic...

Capping poly channel pillars in stacked circuits

Methods and apparatuses having memory cells including a monolithic...

Methods and apparatuses having memory cells including a monolithic...

Capping poly channel pillars in stacked circuits

Lithography methods, methods for forming patterning tools and patte...

Lithography methods, methods for forming patterning tools and patte...

Patents Applicationslast 30 patents

LOW-COST MASK PUNCH FLOW

FLASH MEMORY CHIP WITH SELF ALIGNED ISOLATION FILL BETWEEN PILLARS

RESISTANCE REDUCTION FOR WORD LINES IN MEMORY ARRAYS

METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC...

METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC...

CAPPING POLY CHANNEL PILLARS IN STACKED CIRCUITS

METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC...

LITHOGRAPHY METHODS, METHODS FOR FORMING PATTERNING TOOLS AND PATTE...

LITHOGRAPHY METHODS, METHODS FOR FORMING PATTERNING TOOLS AND PATTE...