Prashant Dubey

Person

Allahabad, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Power gating in stacked die structures
- Patent number 11,374,564
- Issue date Jun 28, 2022
- Xilinx, Inc.
- Prashant Dubey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bit-line repeater insertion architecture
- Patent number 10,891,992
- Issue date Jan 12, 2021
- Synopsys, Inc.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Reset before write architecture and method
- Patent number 10,867,665
- Issue date Dec 15, 2020
- Synopsys, Inc.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Power gating in stacked die structures
- Patent number 10,826,492
- Issue date Nov 3, 2020
- Xilinx, Inc.
- Prashant Dubey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Read-write architecture for low voltage SRAMs
- Patent number 10,790,013
- Issue date Sep 29, 2020
- Synopsys, Inc.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Data storage element and signal processing method
- Patent number 9,602,085
- Issue date Mar 21, 2017
- Synopsys, Inc.
- Prashant Dubey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Controlling timing of negative charge injection to generate reliabl...
- Patent number 9,281,030
- Issue date Mar 8, 2016
- Synopsys, Inc.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for generating negative bitline voltage
- Patent number 8,837,229
- Issue date Sep 16, 2014
- Synopsys, Inc.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Matrix structure oscillator
- Patent number 8,779,862
- Issue date Jul 15, 2014
- STMicroelectronics International N.V.
- Prashant Dubey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory architecture and design methodology with adaptive read
- Patent number 8,737,144
- Issue date May 27, 2014
- STMicroelectronics International N.V.
- Navneet Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Coupled ring oscillator
- Patent number 8,638,175
- Issue date Jan 28, 2014
- STMicroelectronics International N.V.
- Prashant Dubey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus having error detection in sequential logic
- Patent number 8,624,623
- Issue date Jan 7, 2014
- STMicroelectronics International N.V.
- Navneet Gupta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Differential data sensing
- Patent number 8,456,197
- Issue date Jun 4, 2013
- STMicroelectronics International N.V.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Locally synchronous shared BIST architecture for testing embedded m...
- Patent number 8,386,864
- Issue date Feb 26, 2013
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for efficient detection and restoration of data s...
- Patent number 8,352,781
- Issue date Jan 8, 2013
- STMicroelectronics International N.V.
- Akhil Garg
- G11 - INFORMATION STORAGE
Information Patent Grant
Matrix structure oscillator
- Patent number 8,232,843
- Issue date Jul 31, 2012
- STMicroelectronics International N.V.
- Prashant Dubey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Locally synchronous shared BIST architecture for testing embedded m...
- Patent number 8,108,744
- Issue date Jan 31, 2012
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self-repairable memory
- Patent number 8,055,956
- Issue date Nov 8, 2011
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Area efficient memory architecture with decoder self test and debug...
- Patent number 8,046,655
- Issue date Oct 25, 2011
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple embedded memories and testing components for the same
- Patent number 7,954,017
- Issue date May 31, 2011
- STMicroelectronics Pvt. Ltd.
- Amit Kashyap
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable memory architecture with built-in testing mechanism
- Patent number 7,603,603
- Issue date Oct 13, 2009
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated scannable interface for testing memory
- Patent number 7,496,809
- Issue date Feb 24, 2009
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared redundant memory architecture and memory system incorporatin...
- Patent number 7,385,862
- Issue date Jun 10, 2008
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip analysis and computation of transition behavior of embedded...
- Patent number 7,248,066
- Issue date Jul 24, 2007
- STMicroelectronics Pvt. Ltd.
- Ruchir Saraswat
- G01 - MEASURING TESTING
Information Patent Grant
Digital clock generator circuit with built-in frequency and duty cy...
- Patent number 6,650,162
- Issue date Nov 18, 2003
- STMicroelectronics Ltd.
- Prashant Dubey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesizable synchronous static RAM
- Patent number 6,470,475
- Issue date Oct 22, 2002
- STMicroelectronics Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
POWER GATING IN STACKED DIE STRUCTURES
- Publication number 20200076424
- Publication date Mar 5, 2020
- Xilinx, Inc.
- Prashant Dubey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data Storage Element and Signal Processing Method
- Publication number 20160126936
- Publication date May 5, 2016
- Synopsys, Inc.
- Prashant Dubey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling Timing of Negative Charge Injection to Generate Reliabl...
- Publication number 20150170721
- Publication date Jun 18, 2015
- Synopsys, Inc.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT FOR GENERATING NEGATIVE BITLINE VOLTAGE
- Publication number 20140269105
- Publication date Sep 18, 2014
- Synopsys, Inc.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS
- Publication number 20130169360
- Publication date Jul 4, 2013
- STMICROELECTRONICS PVT. LTD.
- Navneet GUPTA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY ARCHITECTURE AND DESIGN METHODOLOGY WITH ADAPTIVE READ
- Publication number 20130170306
- Publication date Jul 4, 2013
- STMICROELECTRONICS PVT. LTD.
- Navneet GUPTA
- G11 - INFORMATION STORAGE
Information Patent Application
MATRIX STRUCTURE OSCILLATOR
- Publication number 20120280756
- Publication date Nov 8, 2012
- STMicroelectronics International N.V
- Prashant Dubey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOCALLY SYNCHRONOUS SHARED BIST ARCHITECTURE FOR TESTING EMBEDDED M...
- Publication number 20120198291
- Publication date Aug 2, 2012
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
DIFFERENTIAL DATA SENSING
- Publication number 20120169378
- Publication date Jul 5, 2012
- STMICROELECTRONICS PVT. LTD.
- Prashant Dubey
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
COUPLED RING OSCILLATOR
- Publication number 20120161883
- Publication date Jun 28, 2012
- STMICROELECTRONICS PVT. LTD.
- Prashant Dubey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MATRIX STRUCTURE OSCILLATOR
- Publication number 20100156543
- Publication date Jun 24, 2010
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM AND METHOD FOR EFFICIENT DETECTION AND RESTORATION OF DATA S...
- Publication number 20100017651
- Publication date Jan 21, 2010
- STMICROELECTRONICS PVT. LTD.
- Akhil Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Locally synchronous shared BIST architecture for testing embedded m...
- Publication number 20080126892
- Publication date May 29, 2008
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
Multiple embedded memories and testing components for the same
- Publication number 20070162793
- Publication date Jul 12, 2007
- STMicroelectronics Pvt, Ltd.
- Amit Kashyap
- G11 - INFORMATION STORAGE
Information Patent Application
Built-in self-repairable memory
- Publication number 20070061653
- Publication date Mar 15, 2007
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED REDUNDANT MEMORY ARCHITECTURE AND MEMORY SYSTEM INCORPORATIN...
- Publication number 20070036011
- Publication date Feb 15, 2007
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
Configurable memory architecture with built-in testing mechanism
- Publication number 20070016826
- Publication date Jan 18, 2007
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED SCANNABLE INTERFACE FOR TESTING MEMORY
- Publication number 20070011521
- Publication date Jan 11, 2007
- Prashant Dubey
- G01 - MEASURING TESTING
Information Patent Application
Area efficient memory architecture with decoder self test and debug...
- Publication number 20070002649
- Publication date Jan 4, 2007
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for BitMap Analysis System for high speed testing...
- Publication number 20060248414
- Publication date Nov 2, 2006
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
On-chip analysis & computation of transition behaviour of embedded...
- Publication number 20050174102
- Publication date Aug 11, 2005
- STMicroelectronics Pvt. Ltd.
- Ruchir Saraswat
- G01 - MEASURING TESTING
Information Patent Application
Synthesizable synchronous static RAM
- Publication number 20020110042
- Publication date Aug 15, 2002
- STMicroelectronic Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
Digital clock generator circuit with built-in frequency and duty cy...
- Publication number 20020079943
- Publication date Jun 27, 2002
- STMicroelectronics Ltd.
- Prashant Dubey
- G06 - COMPUTING CALCULATING COUNTING

Prashant Dubey

Person

Patents Grantslast 30 patents

Power gating in stacked die structures

Bit-line repeater insertion architecture

Reset before write architecture and method

Power gating in stacked die structures

Read-write architecture for low voltage SRAMs

Data storage element and signal processing method

Controlling timing of negative charge injection to generate reliabl...

Circuit for generating negative bitline voltage

Matrix structure oscillator

Memory architecture and design methodology with adaptive read

Coupled ring oscillator

Apparatus having error detection in sequential logic

Differential data sensing

Locally synchronous shared BIST architecture for testing embedded m...

System and method for efficient detection and restoration of data s...

Matrix structure oscillator

Locally synchronous shared BIST architecture for testing embedded m...

Built-in self-repairable memory

Area efficient memory architecture with decoder self test and debug...

Multiple embedded memories and testing components for the same

Configurable memory architecture with built-in testing mechanism

Integrated scannable interface for testing memory

Shared redundant memory architecture and memory system incorporatin...

On-chip analysis and computation of transition behavior of embedded...

Digital clock generator circuit with built-in frequency and duty cy...

Synthesizable synchronous static RAM

Patents Applicationslast 30 patents

POWER GATING IN STACKED DIE STRUCTURES

Data Storage Element and Signal Processing Method

Controlling Timing of Negative Charge Injection to Generate Reliabl...

CIRCUIT FOR GENERATING NEGATIVE BITLINE VOLTAGE

APPARATUS

MEMORY ARCHITECTURE AND DESIGN METHODOLOGY WITH ADAPTIVE READ

MATRIX STRUCTURE OSCILLATOR

LOCALLY SYNCHRONOUS SHARED BIST ARCHITECTURE FOR TESTING EMBEDDED M...

DIFFERENTIAL DATA SENSING

COUPLED RING OSCILLATOR

MATRIX STRUCTURE OSCILLATOR

SYSTEM AND METHOD FOR EFFICIENT DETECTION AND RESTORATION OF DATA S...

Locally synchronous shared BIST architecture for testing embedded m...

Multiple embedded memories and testing components for the same

Built-in self-repairable memory

SHARED REDUNDANT MEMORY ARCHITECTURE AND MEMORY SYSTEM INCORPORATIN...

Configurable memory architecture with built-in testing mechanism

INTEGRATED SCANNABLE INTERFACE FOR TESTING MEMORY

Area efficient memory architecture with decoder self test and debug...

Method and system for BitMap Analysis System for high speed testing...

On-chip analysis & computation of transition behaviour of embedded...

Synthesizable synchronous static RAM

Digital clock generator circuit with built-in frequency and duty cy...