Patent Application
20060248414
The present application claims priority of India Patent Application No. 711/Del/2005 filed Mar. 31, 2005, which is incorporated herein in its entirety by this reference.
The present invention relates to a Bit Map Analysis System (BMAS) for high-speed testing of memories.
The semiconductor industry has intensified its focus on yield issues to meet the challenges of manufacturing devices at sub-nanometer and below. An important step in correcting the existing manufacturing yield issues is finding the defects. For this reason, an important component of a comprehensive test methodology is effective embedded memory testing. Relative to logic circuitry, the redundant nature of a memory structure makes it easier to pinpoint locations of defects, in many cases down to specific transistors.
Recent technology advances in memory built-in-self-test (BIST) have made it the most prevalent methodology for testing embedded memories, and, for BIST, bitmap or failure map is important. Thus, if somehow, a snapshot of the core is taken then by seeing the pattern of the snapshot one can make inferences about the faults present in the address decoder, or Input Output (I/O), or core. This snapshot is known as the Bitmap and is generated by writing some known data on the memory and then reading and comparing each word to see which word location or bit location is failing. This is the raw information used to create the bit map. In
There are several problems that are commonly encountered while generating the bitmap. It is observed that more faults occur at high clock speeds for reading/writing from memories. However, most testers today operate at a very low clock speed as the I/O's for the testers fail at high frequencies. Due to this problem, many faults that should be detected may be missed. The raw data for one word is normally of a good length as it contains the address of the word, the data output of the memory, and the stimuli which were written. Sometimes if the test is running at the tester's frequency, the stimuli and the address information can be left out as by counting the number of clock cycles at which the fault occurred, and one can tell the address and the stimuli. In addition, if the test patterns were run through a tester, there is no need of the address and stimuli information. The data output response of the memory itself is enough. However, sometimes this information is also big and it takes a lot of space to store it as well as to send it out to the tester. The channels through which the tester receives the data are far smaller in number, and normally, only one output is available to pipe the data serially out.
All widely used current methodologies for testing memories treat the memory blocks as macros, and hence, all the faults whether they are in the address decoder or I/O or core of the memory are finally mapped on the core.
Some of the devices used for generating the Bit Map of the embedded memories are as follows:
Serial Pipe Based:
Parallel First-in-First-out (FIFO) Memory Based Bitmap Generator:
This method is an extension to the serial pipe based method. In this method instead of using a serial pipe of one word 23 as shown in
Fail Counter Method:
In this kind of Bit Map generation method, the BIST stops each time during the run when it encounters a fault. Every time the BIST stops, it stores all the raw information about the fault and sends it to the tester and increments the fail counter. In its next run, the BIST stops at the N+1th fault where N is the current value of the counter. Thus, one can generate the bit map with all the information given by the BIST. The problem with this methodology is that this counter is unused if there are very few faults. In addition, if there are a large number of faults, then one needs a very big counter. Also this method needs a lot of time and hardware resources to generate the complete bit map of the memory. In addition, the method does not generate good information in case of marginal errors where the error occurs in one run, and it does not repeat itself in the next run, thus the BIST skips a genuine fault due to this deficiency.
Compression-based methods are another set of techniques that are used to generate a bitmap of a faulty memory. A problem with these methods is that the compression is always lossy; hence, the complete picture is not obtained for the memory. In addition, the hardware needed for compression takes a lot of area, which is not suitable for production units where the bitmap is only needed in case of debugging at the early stage of the Integrated Circuit (IC) product.
Hence, the disadvantages of existing architectures are as follows:
The present invention provides a bit map analysis methodology with a unique architecture, which solves the problems created by the above-mentioned disadvantages. The new architecture has a low area overhead and the device is aimed at providing a faster execution of the diagnostic process.
To obviate the aforesaid drawbacks, an object of the instant invention is to provide a bit map analysis with low area overhead.
Another object of the invention is to reduce the amount of data transaction between the BIST and the tester.
Yet another object of the invention is to reduce the tester clock cycles, due to which the diagnose timings are reduced drastically.
To achieve the aforesaid and other objects, the instant invention provides a Bit Map Analysis System for high-speed memory testing of memory partitioned into small, equal-sized memory segments. The system includes a test engine connected to the memory for generating bitmaps, and a First In First Out (FIFO) memory mechanism having its write port connected to the test engine and its read port connected to a tester. The FIFO memory mechanism contains at least one FIFO memory segment equivalent to the size of said memory segments. The test engine sequentially generates and verifies the bitmaps of each of said memory segment.
A serial pipe of predetermined size is also provided that is connected to the read port of said FIFO mechanism for reading and transmitting the test results. In a preferred embodiment, the memory core is partitioned into equal sized segments.
The test engine of the present invention may preferably include a state machine connected to the FIFO mechanism and a tester for controlling and managing the handshake signals, a Built-in-Self-Test (BIST) connected to the state machine for generating bitmap for the memory core and FIFO, a first counter connected to the state machine for counting up to total Bits/N, a second counter connected to the state machine for counting up to total Words/M, a programmable read address sequence generator (PRASG) serially interfaced to the tester for providing address sequence generation.
A method of the present invention for high speed testing of memory includes the steps of partitioning a memory core into smaller equal sized segments, sequentially generating bitmaps for the memory segments, storing the bitmap result of each memory segment in a FIFO memory segment equivalent to the size of the memory segments after being extracted for analysis before generating the bitmap for next memory segment. Preferably, the stored results are transmitted to a tester using a serial pipe of predetermined size.
The solution provided through BMAS strategy is worth using inside the embedded memories whether they are asynchronous or synchronous, static or dynamic, volatile or non-volatile. This invention reduces the amount of data transaction between the BIST and the tester. Hence, the tester clock cycle reduces drastically, resulting in reduced diagnostic process time.
The present invention is described with the help of accompanying drawings:
In the current approach of analyzing memory faults and creating a bitmap, a FIFO is used as an interface between a BIST and a tester. The invention divides a big memory core into many small logical memory cores and generates a bit map for the same that can be stored in a smaller FIFO.
OPCODE LOADER: It is generally a sequence of instructions run by the BIST 33 and is a combination of various March elements. Any March element is further a combination of some write or read operations. Thus, a March element forms a complete stimulus, by which one can tell, what operations have been done on the memory and what can be the expected data. Thus, the opcode loader loads the background data to be written as well as the expected data to be taken for each FIFO 31, in terms of inverted or non-inverted data background. The data background is sent only once at the beginning of the instructions and remains constant for all the March elements. Only the expected inverted data or non-inverted data as well as the number of operations in one March element change with each new March element. This reduces the need to transfer the stimuli along with the bitmap. Thus, the expected data bitmap at the tester can be formed.
FIFO: The FIFO 31 is used to represent a part of the RAM core 30. The write port is connected to the BIST 33 while the read part is connected to the tester. Thus, BIST 33 writes into the first word of the FIFO 31 when it makes the first valid measurement. If the result of the memory word is false, it stores logic 1 in place of that bit, otherwise logic 0 is stored. This activity is repeated until all the words in the current window are over. As the BIST 33 does not stop during one March element run, the number of parallel FIFOs needed is equal to the number of maximum operations in any of the March elements.
STATE MACHINE: As soon as the FIFO 31 is full, the state machine 36 generates a flag for the tester to start reading the bitmap. BIST 33 runs for all the possible windows, one by one. As soon as the FIFO 31 is full, the state machine 36 sends a signal to the tester to read the stored bitmap of the current window. In addition, the BIST 33 continues to run the March element until all the words of the memory 30 are exhausted. At the last word of the memory 30, the BIST 33 waits for the tester to complete reading of the FIFO 31. Once all the data has been read, the state machine 36 starts the BIST 33 from beginning of the March element of interest and makes the comparison accordingly.
PRASG: The PRASG 37 is the block that generates the address on which the read operation is performed on the ROM core 30. The sequence generated can be a pseudo random pattern, which can be programmed by reseeding at the beginning of the memory test. The deterministic sequence can be programmed up to K number of read cycles per address, where the address sequence can be defined for M number of words for each read cycle.
COUNTERS: The counters 34 and 35 are used to run the BIST 33 for as many times as there are possible windows. The number of runs required is obtained by dividing the number of words in the memory by the number of words in the FIFO 31 chosen.
SERIAL PIPE: The serial pipe 32 is the interface in the parallel domain of the BIST 33 and the serial domain of the tester. If there are more pins that can be dedicated for the debug and diagnostics purposes, one can reduce the length of the serial pipe 32. The clock of the serial pipe 32 is that of the tester clock speed.
An approach or exemplary operation of the system of
Thus, at the end of this operation or testing process, the tester has the complete bitmap of the memory. In addition, the stimuli need not be stored along with the faulty bit information stored on chip. The stimulus is known to the tester. The bitmap has to be different for each comparison of the same word. Thus, if there are k read/write operations to be done in one March element on the BIST and where out of k, only x one operations will be measured by the BIST, x identical FIFOs are needed for one set of bitmap data.
While there have been described above the principles of the present invention in conjunction with specific memory architectures and methods of operation, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
| Number | Date | Country | Kind |
|---|---|---|---|
| 711/DEL/2005 | Mar 2005 | IN | national |
