Prayag Bhanubhai Patel

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Flip-flop with reduced retention voltage
- Patent number 9,673,786
- Issue date Jun 6, 2017
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low leakage retention register tray
- Patent number 9,178,496
- Issue date Nov 3, 2015
- QUALCOMM Incorporated
- Ramaprasath Vilangudipitchai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Length-of-diffusion protected circuit and method of design
- Patent number 9,093,995
- Issue date Jul 28, 2015
- QUALCOMM Incorporated
- Kashyap Ramachandra Bellur
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low leakage retention register tray
- Patent number 8,975,934
- Issue date Mar 10, 2015
- QUALCOMM Incorporated
- Ramaprasath Vilangudipitchai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Shared-diffusion standard cell architecture
- Patent number 8,836,040
- Issue date Sep 16, 2014
- QUALCOMM Incorporated
- Pratyush Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Standard cell architecture using double poly patterning for multi V...
- Patent number 8,610,176
- Issue date Dec 17, 2013
- QUALCOMM Incorporated
- Prayag B. Patel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for characterizing and reducing proximity effe...
- Patent number 8,584,075
- Issue date Nov 12, 2013
- QUALCOMM Incorporated
- Animesh Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques providing fiducial markers for failure analysis
- Patent number 8,420,410
- Issue date Apr 16, 2013
- QUALCOMM Incorporated
- Michael Laisne
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Yield based flop hold time and setup time definition
- Patent number 8,356,263
- Issue date Jan 15, 2013
- QUALCOMM Incorporated
- Xiaonan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods using improved clock gating cells
- Patent number 8,030,982
- Issue date Oct 4, 2011
- QUALCOMM Incorporated
- Animesh Datta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Logic device and method supporting scan test
- Patent number 7,992,062
- Issue date Aug 2, 2011
- QUALCOMM Incorporated
- Martin Saint-Laurent
- G01 - MEASURING TESTING
Information Patent Grant
System and method for tolerating data link faults in a packet commu...
- Patent number 7,352,694
- Issue date Apr 1, 2008
- Applied Micro Circuits Corporation
- Philip Michael Clovis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable switch fabric interface bandwidth system and method
- Patent number 7,298,754
- Issue date Nov 20, 2007
- Applied Micro Circuits Corporation
- Kirk Alvin Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for programming cell packet headers
- Patent number 7,298,756
- Issue date Nov 20, 2007
- Applied Micro Circuits Corporation
- Kirk Alvin Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for tolerating data link faults in communications...
- Patent number 7,221,652
- Issue date May 22, 2007
- Applied Micro Circuits Corporation
- Sushil Kumar Singh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
LOW LEAKAGE RETENTION REGISTER TRAY
- Publication number 20150130524
- Publication date May 14, 2015
- Qualcomm, Incorporated.
- Ramaprasath Vilangudipitchai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LENGTH-OF-DIFFUSION PROTECTED CIRCUIT AND METHOD OF DESIGN
- Publication number 20140354338
- Publication date Dec 4, 2014
- Kashyap Ramachandra Bellur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLIP-FLOP WITH REDUCED RETENTION VOLTAGE
- Publication number 20140306735
- Publication date Oct 16, 2014
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW LEAKAGE RETENTION REGISTER TRAY
- Publication number 20140253197
- Publication date Sep 11, 2014
- QUALCOMM Incorporated
- Ramaprasath Vilangudipitchai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED-DIFFUSION STANDARD CELL ARCHITECTURE
- Publication number 20140124868
- Publication date May 8, 2014
- QUALCOMM Incorporated
- Pratyush Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AREA EFFICIENT GRIDDED POLYSILICON LAYOUTS
- Publication number 20130032885
- Publication date Feb 7, 2013
- QUALCOMM Incorporated
- Chethan Swamynathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
YIELD BASED FLOP HOLD TIME AND SETUP TIME DEFINITION
- Publication number 20130007681
- Publication date Jan 3, 2013
- QUALCOMM Incorporated
- Xiaonan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Characterizing and Reducing Proximity Effe...
- Publication number 20120210284
- Publication date Aug 16, 2012
- QUALCOMM Incorporated
- Animesh Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Standard Cell Architecture Using Double Poly Patterning for Multi V...
- Publication number 20120180016
- Publication date Jul 12, 2012
- QUALCOMM Incorporated
- PR Chidambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES PROVIDING FIDUCIAL MARKERS FOR FAILURE ANALYSIS
- Publication number 20110164808
- Publication date Jul 7, 2011
- QUALCOMM Incorporated
- Michael Laisne
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Systems and Methods Using Improved Clock Gating Cells
- Publication number 20100109747
- Publication date May 6, 2010
- QUALCOMM Incorporated
- Animesh Datta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Logic device and method supporting scan test
- Publication number 20070300108
- Publication date Dec 27, 2007
- Martin Saint-Laurent
- G01 - MEASURING TESTING

Prayag Bhanubhai Patel

Person

Patents Grantslast 30 patents

Flip-flop with reduced retention voltage

Low leakage retention register tray

Length-of-diffusion protected circuit and method of design

Low leakage retention register tray

Shared-diffusion standard cell architecture

Standard cell architecture using double poly patterning for multi V...

Method and apparatus for characterizing and reducing proximity effe...

Techniques providing fiducial markers for failure analysis

Yield based flop hold time and setup time definition

Systems and methods using improved clock gating cells

Logic device and method supporting scan test

System and method for tolerating data link faults in a packet commu...

Configurable switch fabric interface bandwidth system and method

System and method for programming cell packet headers

System and method for tolerating data link faults in communications...

Patents Applicationslast 30 patents

LOW LEAKAGE RETENTION REGISTER TRAY

LENGTH-OF-DIFFUSION PROTECTED CIRCUIT AND METHOD OF DESIGN

FLIP-FLOP WITH REDUCED RETENTION VOLTAGE

LOW LEAKAGE RETENTION REGISTER TRAY

SHARED-DIFFUSION STANDARD CELL ARCHITECTURE

AREA EFFICIENT GRIDDED POLYSILICON LAYOUTS

YIELD BASED FLOP HOLD TIME AND SETUP TIME DEFINITION

Method and Apparatus for Characterizing and Reducing Proximity Effe...

Standard Cell Architecture Using Double Poly Patterning for Multi V...

TECHNIQUES PROVIDING FIDUCIAL MARKERS FOR FAILURE ANALYSIS

Systems and Methods Using Improved Clock Gating Cells

Logic device and method supporting scan test