Promod KUMAR

Person

Ghaziabad, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Memory architecture supporting both conventional memory access mode...
- Patent number 12,361,982
- Issue date Jul 15, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive word line underdrive control for an in-memory compute oper...
- Patent number 12,354,644
- Issue date Jul 8, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Kedar Janardan Dhori
- G11 - INFORMATION STORAGE
Information Patent Grant
Tuning of read/write cycle time delay for a memory circuit dependen...
- Patent number 12,353,341
- Issue date Jul 8, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Bhupender Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Silicon-on-insulator semiconductor device with a static random acce...
- Patent number 12,328,858
- Issue date Jun 10, 2025
- STMicroelectronics France
- Olivier Weber
- G11 - INFORMATION STORAGE
Information Patent Grant
Computing system power management device, system and method
- Patent number 12,292,780
- Issue date May 6, 2025
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective bit line clamping control for an in-memory compute operat...
- Patent number 12,237,007
- Issue date Feb 25, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Kedar Janardan Dhori
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit-cell architecture based in-memory compute
- Patent number 12,183,424
- Issue date Dec 31, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive body bias management for an in-memory compute operation wh...
- Patent number 12,176,025
- Issue date Dec 24, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self test circuit for segmented static random access memor...
- Patent number 12,170,120
- Issue date Dec 17, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Hitesh Chawla
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with fast, controlled peak current, power efficient array rese...
- Patent number 12,159,689
- Issue date Dec 3, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Praveen Kumar Verma
- G11 - INFORMATION STORAGE
Information Patent Grant
Serial word line actuation with linked source voltage supply modula...
- Patent number 12,087,356
- Issue date Sep 10, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Modular memory architecture with gated sub-array operation dependen...
- Patent number 12,046,324
- Issue date Jul 23, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive bit line overdrive control for an in-memory compute operat...
- Patent number 11,984,151
- Issue date May 14, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Computing system power management device, system and method
- Patent number 11,726,543
- Issue date Aug 15, 2023
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fail safe adaptive voltage/frequency system
- Patent number 8,269,545
- Issue date Sep 18, 2012
- STMicroelectronics International N.V.
- Nitin Chawla
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Fail-safe high speed level shifter for wide supply voltage range
- Patent number 8,218,377
- Issue date Jul 10, 2012
- STMicroelectronics Pvt. Ltd.
- Amit Tandon
- G11 - INFORMATION STORAGE
Information Patent Grant
Fail safe adaptive voltage/frequency system
- Patent number 8,154,335
- Issue date Apr 10, 2012
- STMicroelectronics Pvt. Ltd.
- Nitin Chawla
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
High voltage switch with reduced voltage stress at output stage
- Patent number 7,750,689
- Issue date Jul 6, 2010
- STMicroelectronics, PVT. Ltd.
- Vikas Rana
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Nonvolatile memory and high speed memory test method
- Patent number 6,438,048
- Issue date Aug 20, 2002
- STMicroelectronics S.r.l.
- Promod Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory test method and nonvolatile memory with low error masking pr...
- Patent number 6,282,134
- Issue date Aug 28, 2001
- STMicroelectronics S.r.l.
- Promod Kumar
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...
- Publication number 20250174269
- Publication date May 29, 2025
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE
- Publication number 20250078883
- Publication date Mar 6, 2025
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20250069678
- Publication date Feb 27, 2025
- STMicroelectronics International N.V.
- Hitesh CHAWLA
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...
- Publication number 20250054529
- Publication date Feb 13, 2025
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...
- Publication number 20250054528
- Publication date Feb 13, 2025
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...
- Publication number 20240395319
- Publication date Nov 28, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUT...
- Publication number 20240177769
- Publication date May 30, 2024
- STMicroelectronics International N.V.
- Promod KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
TUNING OF READ/WRITE CYCLE TIME DELAY FOR A MEMORY CIRCUIT DEPENDEN...
- Publication number 20240143239
- Publication date May 2, 2024
- STMicroelectronics International N.V.
- Bhupender SINGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...
- Publication number 20240112748
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Tanuj KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEM...
- Publication number 20240112728
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20240069096
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Bhupender SINGH
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...
- Publication number 20240071429
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20240071546
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Hitesh CHAWLA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...
- Publication number 20240071439
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SILICON-ON-INSULATOR SEMICONDUCTOR DEVICE WITH A STATIC RANDOM ACCE...
- Publication number 20240015945
- Publication date Jan 11, 2024
- STMicroelectronics S.A.
- Olivier Weber
- G11 - INFORMATION STORAGE
Information Patent Application
BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OP...
- Publication number 20230410892
- Publication date Dec 21, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...
- Publication number 20230410862
- Publication date Dec 21, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BIT LINE VOLTAGE CLAMPING READ CIRCUIT FOR AN IN-MEMORY COMPUTE OPE...
- Publication number 20230386566
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...
- Publication number 20230386565
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPER...
- Publication number 20230386564
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTING SYSTEM POWER MANAGEMENT DEVICE, SYSTEM AND METHOD
- Publication number 20230350483
- Publication date Nov 2, 2023
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE
- Publication number 20230102492
- Publication date Mar 30, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
MODULAR MEMORY ARCHITECTURE WITH GATED SUB-ARRAY OPERATION DEPENDEN...
- Publication number 20230051672
- Publication date Feb 16, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WH...
- Publication number 20230012567
- Publication date Jan 19, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...
- Publication number 20230018420
- Publication date Jan 19, 2023
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...
- Publication number 20230008833
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE BIT LINE OVERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...
- Publication number 20230009329
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...
- Publication number 20230012303
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPER...
- Publication number 20230008275
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTING SYSTEM POWER MANAGEMENT DEVICE, SYSTEM AND METHOD
- Publication number 20210181828
- Publication date Jun 17, 2021
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING

Promod KUMAR

Person

Patents Grantslast 30 patents

Memory architecture supporting both conventional memory access mode...

Adaptive word line underdrive control for an in-memory compute oper...

Tuning of read/write cycle time delay for a memory circuit dependen...

Silicon-on-insulator semiconductor device with a static random acce...

Computing system power management device, system and method

Selective bit line clamping control for an in-memory compute operat...

Bit-cell architecture based in-memory compute

Adaptive body bias management for an in-memory compute operation wh...

Built-in self test circuit for segmented static random access memor...

SRAM with fast, controlled peak current, power efficient array rese...

Serial word line actuation with linked source voltage supply modula...

Modular memory architecture with gated sub-array operation dependen...

Adaptive bit line overdrive control for an in-memory compute operat...

Computing system power management device, system and method

Fail safe adaptive voltage/frequency system

Fail-safe high speed level shifter for wide supply voltage range

Fail safe adaptive voltage/frequency system

High voltage switch with reduced voltage stress at output stage

Nonvolatile memory and high speed memory test method

Memory test method and nonvolatile memory with low error masking pr...

Patents Applicationslast 30 patents

SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...

BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...

SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...

SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...

BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUT...

TUNING OF READ/WRITE CYCLE TIME DELAY FOR A MEMORY CIRCUIT DEPENDEN...

AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...

ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEM...

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...

SILICON-ON-INSULATOR SEMICONDUCTOR DEVICE WITH A STATIC RANDOM ACCE...

BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OP...

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...

BIT LINE VOLTAGE CLAMPING READ CIRCUIT FOR AN IN-MEMORY COMPUTE OPE...

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...

ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPER...

COMPUTING SYSTEM POWER MANAGEMENT DEVICE, SYSTEM AND METHOD

BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE

MODULAR MEMORY ARCHITECTURE WITH GATED SUB-ARRAY OPERATION DEPENDEN...

ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WH...

SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...

SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...

ADAPTIVE BIT LINE OVERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...

SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...

ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPER...

COMPUTING SYSTEM POWER MANAGEMENT DEVICE, SYSTEM AND METHOD