Pushkar Ranade

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Active regions with compatible dielectric layers
- Patent number 9,847,420
- Issue date Dec 19, 2017
- Intel Corporation
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Active regions with compatible dielectric layers
- Patent number 9,646,822
- Issue date May 9, 2017
- Intel Corporation
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Active regions with compatible dielectric layers
- Patent number 9,515,142
- Issue date Dec 6, 2016
- Intel Corporation
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Active regions with compatible dielectric layers
- Patent number 9,397,165
- Issue date Jul 19, 2016
- Intel Corporation
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Active regions with compatible dielectric layers
- Patent number 9,287,364
- Issue date Mar 15, 2016
- Intel Corporation
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-abrupt semiconductor junction profile
- Patent number 8,394,687
- Issue date Mar 12, 2013
- Intel Corporation
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming CMOS transistors with dual-metal silicide formed...
- Patent number 7,861,406
- Issue date Jan 4, 2011
- Intel Corporation
- Saurabh Lodha
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Metal and alloy silicides on a single silicon wafer
- Patent number 7,750,471
- Issue date Jul 6, 2010
- Intel Corporation
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming improved EPI fill on narrow isolation bounded so...
- Patent number 7,691,752
- Issue date Apr 6, 2010
- Intel Corporation
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS device with dual-epi channels and self-aligned contacts
- Patent number 7,598,142
- Issue date Oct 6, 2009
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deposition of hafnium oxide and/or zirconium oxide and fabrication...
- Patent number 7,566,938
- Issue date Jul 28, 2009
- International Business Machines Corporation
- Cyril Cabral, Jr.
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method to produce highly doped polysilicon thin films
- Patent number 7,138,307
- Issue date Nov 21, 2006
- Intel Corporation
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deposition of hafnium oxide and/or zirconium oxide and fabrication...
- Patent number 6,982,230
- Issue date Jan 3, 2006
- International Business Machines Corporation
- Cyril Cabral, Jr.
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...
- Publication number 20240222321
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...
- Publication number 20240222326
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING ROUTING ACROSS LAYERS OF CHANN...
- Publication number 20240222271
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR INCLUDING WIDE BAND GAP MATERIALS
- Publication number 20240222438
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR IN A SILICON CARBIDE LAYER AND A TRANSISTOR IN A GALLIUM...
- Publication number 20240222469
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COUPLING A LAYER OF SILICON CARBIDE WITH AN ADJACENT LAYER
- Publication number 20240222435
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAL SHARED GATE HIGH-DRIV...
- Publication number 20240222520
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC RANDOM-ACCESS MEMORY USING WIDE BAND GAP MATERIALS
- Publication number 20240224504
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING BIT-COST SCALING WITH RELAXED...
- Publication number 20240224508
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...
- Publication number 20240222328
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MODULAR MEMORY BLOCKS FOR INTEGRATED CIRCUIT DEVICES
- Publication number 20240222347
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING LOOKUP TABLE DECODERS FOR FPGAS
- Publication number 20240222276
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICES IN A SILICON CARBIDE LAYER COUPLED WITH DEVICES IN A GALLIU...
- Publication number 20240222228
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE POWER DELIVERY AND SI...
- Publication number 20240215222
- Publication date Jun 27, 2024
- Intel Corporation
- Abhishek Anil SHARMA
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE CAPACITORS
- Publication number 20240215256
- Publication date Jun 27, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN SEMI-METALS FOR LOW TEMPERATURE CONDUCTION
- Publication number 20240113025
- Publication date Apr 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BURIED VIA THROUGH FRONT-SIDE AND BACK-SIDE METALLIZATION LAYERS WI...
- Publication number 20240105584
- Publication date Mar 28, 2024
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLID STATE ELECTROLYTES FOR BACKEND SUPERCAPACITORS
- Publication number 20240105585
- Publication date Mar 28, 2024
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNMENT LAYER WITH LOW-K MATERIAL PROXIMATE TO VIAS
- Publication number 20240105635
- Publication date Mar 28, 2024
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRIM PATTERNING FOR FORMING ANGLED TRANSISTORS
- Publication number 20240105798
- Publication date Mar 28, 2024
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW TEMPERATURE VARACTORS USING VARIABLE CAPACITANCE MATERIALS
- Publication number 20240105860
- Publication date Mar 28, 2024
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON CARBIDE POWER DEVICES INTEGRATED WITH SILICON LOGIC DEVICES
- Publication number 20240105700
- Publication date Mar 28, 2024
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECONSTITUTED WAFER WITH SIDE-STACKED INTEGRATED CIRCUIT DIE
- Publication number 20240105677
- Publication date Mar 28, 2024
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FERROELECTRIC TUNNEL JUNCTION DEVICES FOR LOW VOLTAGE AND LOW TEMPE...
- Publication number 20240105811
- Publication date Mar 28, 2024
- Intel Corporation
- Abhishek Anil Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
TCAM WITH HYSTERETIC OXIDE MEMORY CELLS
- Publication number 20240105248
- Publication date Mar 28, 2024
- Intel Corporation
- Abhishek Anil Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
LOW TEMPERATURE CAPACITIVELY COUPLED DEVICE FOR LOW NOISE CIRCUITS
- Publication number 20240105582
- Publication date Mar 28, 2024
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL THROUGH-SILICON WAVEGUIDE FABRICATION METHOD AND TOPOLOGIES
- Publication number 20240103216
- Publication date Mar 28, 2024
- Intel Corporation
- Sagar SUTHRAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL PN JUNCTION PHOTONICS MODULATORS WITH BACKSIDE CONTACTS AN...
- Publication number 20240103304
- Publication date Mar 28, 2024
- Intel Corporation
- Sagar SUTHRAM
- G02 - OPTICS
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH ANGLED INTERCONNECTS
- Publication number 20240105596
- Publication date Mar 28, 2024
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID MANUFACTURING OF ACCESS TRANSISTORS FOR MEMORY
- Publication number 20240098965
- Publication date Mar 21, 2024
- Intel Corporation
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE

Pushkar Ranade

Person

Patents Grantslast 30 patents

Active regions with compatible dielectric layers

Active regions with compatible dielectric layers

Active regions with compatible dielectric layers

Active regions with compatible dielectric layers

Active regions with compatible dielectric layers

Ultra-abrupt semiconductor junction profile

Method of forming CMOS transistors with dual-metal silicide formed...

Metal and alloy silicides on a single silicon wafer

Methods of forming improved EPI fill on narrow isolation bounded so...

CMOS device with dual-epi channels and self-aligned contacts

Deposition of hafnium oxide and/or zirconium oxide and fabrication...

Method to produce highly doped polysilicon thin films

Deposition of hafnium oxide and/or zirconium oxide and fabrication...

Patents Applicationslast 30 patents

PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...

PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...

INTEGRATED CIRCUIT STRUCTURES HAVING ROUTING ACROSS LAYERS OF CHANN...

TRANSISTOR INCLUDING WIDE BAND GAP MATERIALS

TRANSISTOR IN A SILICON CARBIDE LAYER AND A TRANSISTOR IN A GALLIUM...

COUPLING A LAYER OF SILICON CARBIDE WITH AN ADJACENT LAYER

INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAL SHARED GATE HIGH-DRIV...

DYNAMIC RANDOM-ACCESS MEMORY USING WIDE BAND GAP MATERIALS

INTEGRATED CIRCUIT STRUCTURES HAVING BIT-COST SCALING WITH RELAXED...

PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...

MODULAR MEMORY BLOCKS FOR INTEGRATED CIRCUIT DEVICES

INTEGRATED CIRCUIT STRUCTURES HAVING LOOKUP TABLE DECODERS FOR FPGAS

DEVICES IN A SILICON CARBIDE LAYER COUPLED WITH DEVICES IN A GALLIU...

INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE POWER DELIVERY AND SI...

INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE CAPACITORS

ULTRA-THIN SEMI-METALS FOR LOW TEMPERATURE CONDUCTION

BURIED VIA THROUGH FRONT-SIDE AND BACK-SIDE METALLIZATION LAYERS WI...

SOLID STATE ELECTROLYTES FOR BACKEND SUPERCAPACITORS

SELF-ALIGNMENT LAYER WITH LOW-K MATERIAL PROXIMATE TO VIAS

TRIM PATTERNING FOR FORMING ANGLED TRANSISTORS

LOW TEMPERATURE VARACTORS USING VARIABLE CAPACITANCE MATERIALS

SILICON CARBIDE POWER DEVICES INTEGRATED WITH SILICON LOGIC DEVICES

RECONSTITUTED WAFER WITH SIDE-STACKED INTEGRATED CIRCUIT DIE

FERROELECTRIC TUNNEL JUNCTION DEVICES FOR LOW VOLTAGE AND LOW TEMPE...

TCAM WITH HYSTERETIC OXIDE MEMORY CELLS

LOW TEMPERATURE CAPACITIVELY COUPLED DEVICE FOR LOW NOISE CIRCUITS

VERTICAL THROUGH-SILICON WAVEGUIDE FABRICATION METHOD AND TOPOLOGIES

VERTICAL PN JUNCTION PHOTONICS MODULATORS WITH BACKSIDE CONTACTS AN...

INTEGRATED CIRCUIT DEVICES WITH ANGLED INTERCONNECTS

HYBRID MANUFACTURING OF ACCESS TRANSISTORS FOR MEMORY