Patent Application
20250201767
Electronic circuits when commonly fabricated on a wafer of semiconductor material, such as silicon, are called integrated circuits (ICs). The wafer with such ICs is typically cut into numerous individual dies. The dies may be packaged into an IC package containing one or more dies along with other electronic components such as resistors, capacitors, and inductors. The IC package may be integrated onto an electronic system, such as a consumer electronic system, or servers, such as mainframes.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
For purposes of illustrating IC packages described herein, it is important to understand phenomena that may come into play during assembly and packaging of ICs. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.
The trend in the computer industry is to utilize multiple processors in large servers, the multiple processors being coupled together in a single package, such as a Multi-Chip Module (MCM). The multiple processors along with other IC dies containing memory circuits (e.g., cache memory circuits, high-bandwidth memory circuits, etc.) are interconnected by high-speed data buses in the package substrate of the MCM, for example, to enable the totality of processors to operate together. However, current technology in such MCMs is inherently limited in its ability to scale to the bandwidth/distance requirements of next generation servers that could have signal speeds greater than 10 GHz and/or data speeds of 3-10 Terabytes per second. The limitations are primarily associated with bandwidth reduction, signal delay, signal loss, and signal distortion due to various reasons, one of which is the configuration in which the multiple processors are coupled together inside the package.
Current packaging architecture, whether 2D, 2.5D or 3D, utilizes multiple IC dies that are oriented parallel to each other and interconnected by various kinds of interconnects, such as copper microbumps, solder balls, etc. In a general sense, any typical IC die consists of a substrate, an active region in the substrate comprising transistors and other active circuitry, and a metallization stack over the substrate, sharing a contact area with the active region. The metallization stack is the region of the IC die in which the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with conductive traces and conductive vias. Common metals used for the conductive traces and conductive vias are copper and aluminum. The metallization stack typically includes contact pads, insulating layers (e.g., interlayer dielectric (ILD) materials such as silicon oxide), conductive layers comprising the conductive traces, and bonding sites for chip-to-chip or chip-to-package connections. Modern IC dies may include more than 10 conductive layers in the metallization stack.
Conventionally, various such IC dies may be stacked within a package in various ways: (1) back-to-back, in which the substrate of one IC die is in direct contact with the substrate of another IC die; (2) back-to-front, in which the substrate of one IC die is in direct contact with the metallization stack of the other IC die; and (3) front-to-front, in which the metallization stacks of the two IC dies are in direct contact. In all these configurations, the IC dies are mutually parallel to each other, with the active circuitry disposed in planes parallel to the contacting areas of adjacent IC dies. Such architecture suffers from certain inherent limitations. For example, compute IC dies comprising high-performance compute circuitry that generates a lot of heat have to be placed on the top of any such stack so that heat can be dissipated properly. Such placement limits the number of high-power compute IC dies that can be placed in a package having a limited (or constrained) footprint.
Microelectronic assemblies disclosed herein may include IC dies that are vertically stacked and electrically coupled at a lateral edge (e.g., stacked back-to-back, back-to-front, or front-to-front and rotated 90 degrees) to a surface of a base IC die. In particular, a microelectronic assembly disclosed herein may include an IC die coupled to a base IC die by interconnects on a first surface of the IC die and a second surface of the base IC die such that the first surface is in contact with the second surface, and the IC die includes a substrate attached to a metallization stack along a planar interface that is orthogonal to the first surface. The metallization stack of the IC die may include a plurality of layers of conductive traces in a dielectric material, and the interconnects may be coupled to the conductive traces exposed on the first surface. The IC die may be further electrically coupled to VR circuitry that may be a VR die coupled to the surface of the base IC die or may be integrated in the base IC die. In some embodiments, the interconnects may include oxide-oxide bonds and metal-metal bonds, the metal-metal bonds including first bond-pads in the first IC dies and second bond-pads in the second IC die, where the first bond-pads include portions of the conductive traces exposed on the first surface.
Accordingly, microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces and a conductive via having a portion exposed at the third surface; a second IC die having a fourth surface with a conductive contact, the second IC die electrically coupled to the first IC die by an interconnect, wherein the interconnect includes the portion of the conductive via exposed at the third surface of the first IC die electrically coupled by solder to the conductive contact at the fourth surface of the second IC die.
Each of the structures, assemblies, packages, methods, devices, and systems of the present disclosure may have several innovative aspects, no single one of which is solely responsible for all the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.
The terms “circuit” and “circuitry” mean one or more passive and/or active electrical and/or electronic components that are arranged to cooperate with one another to provide a desired function. The terms also refer to analog circuitry, digital circuitry, hard wired circuitry, programmable circuitry, microcontroller circuitry and/or any other type of physical hardware electrical and/or electronic component.
The term “integrated circuit” means a circuit that is integrated into a monolithic semiconductor or analogous material.
In some embodiments, the IC dies disclosed herein may include substantially monocrystalline semiconductors, such as silicon or germanium, as a base material (e.g., substrate, body) on which integrated circuits are fabricated with traditional semiconductor processing methods. The semiconductor base material may include, for example, N-type pr P-type materials. Dies may include, for example, a crystalline base material formed using a bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure. In some other embodiments, the base material of one or more of the IC dies may include alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-N, group III-V, group II-VI, or group IV materials. In yet other embodiments, the base material may include compound semiconductors, for example, with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In yet other embodiments, the base material may include an intrinsic IV or III-V semiconductor material or alloy, not intentionally doped with any electrically active impurity; in alternate embodiments, nominal impurity dopant levels may be present. In still other embodiments, dies may include a non-crystalline material, such as polymers; for example, the base material may include silica-filled epoxy. In other embodiments, the base material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, the base material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although a few examples of the material for dies are described here, any material or structure that may serve as a foundation (e.g., base material) upon which IC circuits and structures as described herein may be built falls within the spirit and scope of the present disclosure.
Unless described otherwise, IC dies described herein include one or more IC structures (or, simply, “ICs”) implementing (i.e., configured to perform) certain functionality. In one such example, the term “memory die” may be used to describe a die that includes one or more ICs implementing memory circuitry (e.g., ICs implementing one or more of memory devices, memory arrays, control logic configured to control the memory devices and arrays, etc.). In another such example, the term “compute die” may be used to describe a die that includes one or more ICs implementing logic/compute circuitry (e.g., ICs implementing one or more of I/O functions, arithmetic operations, pipelining of data, etc.).
In another example, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die.” Note that the terms “chip,” “die,” and “IC die” are used interchangeably herein.
The term “optical structure” includes arrangements of forms fabricated in ICs to receive, transform and/or transmit optical signals as described herein. It may include optical conductors such as waveguides, electromagnetic radiation sources such as lasers and light-emitting diodes (LEDs) and electro-optical devices such as photodetectors.
In various embodiments, any photonic IC (PIC) described herein may include a semiconductor material, for example, N-type or P-type materials. The PIC may include, for example, a crystalline base material formed using a bulk silicon (or other bulk semiconductor material) or a SOI structure (or, in general, a semiconductor-on-insulator structure). In some embodiments, the PIC may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, lithium niobite, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide, or other combinations of group III-N or group IV materials. In some embodiments, the PIC may include a non-crystalline material, such as polymers. In some embodiments, the PIC may be formed on a printed circuit board (PCB). In some embodiments, the PIC may be inhomogeneous, including a carrier material (such as glass or silicon carbide) as a base material with a thin semiconductor layer over which is an active side comprising transistors and like components. Although a few examples of the material for the PIC are described here, any material or structure that may serve as a foundation upon which the PIC may be built falls within the spirit and scope of the present disclosure.
The term “insulating” means “electrically insulating,” the term “conducting” means “electrically conducting,” unless otherwise specified. With reference to optical signals and/or devices, components and elements that operate on or using optical signals, the term “conducting” can also mean “optically conducting.”
The terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc.
The term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide.
The term “insulating material” or “insulator” (also called herein as “dielectric material” or “dielectric”) refers to solid materials (and/or liquid materials that solidify after processing as described herein) that are substantially electrically nonconducting. They may include, as examples and not as limitations, organic polymers and plastics, and inorganic materials such as ionic crystals, porcelain, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and alumina or a combination thereof. They may include dielectric materials, high polarizability materials, and/or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Further examples of insulating materials are underfills and molds or mold-like materials used in packaging applications, including for example, materials used in organic interposers, package supports and other such components.
In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those that are monolithically integrated within an IC, mounted on an IC, or those connected to an IC. The ICs described herein may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The ICs described herein may be employed in a single IC die or as part of a chipset for executing one or more related functions in a computer.
In various embodiments of the present disclosure, transistors described herein may be field-effect transistors (FETs), e.g., MOSFETs. In many embodiments, an FET is a four-terminal device. In silicon-on-insulator, or nanoribbon, or gate all-around (GAA) FET, the FET is a three-terminal device that includes source, drain, and gate terminals and uses electric field to control current flowing through the device. A FET typically includes a channel material, a source region and a drain regions provided in and/or over the channel material, and a gate stack that includes a gate electrode material, alternatively referred to as a “work function” material, provided over a portion of the channel material (the “channel portion”) between the source and the drain regions, and optionally, also includes a gate dielectric material between the gate electrode material and the channel material.
In a general sense, an “interconnect” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, facilitating communication of electrical signals between them; an optical interconnect provides optical connectivity between two optical components, facilitating communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are included in the term “interconnect.” The nature of the interconnect being described is to be understood herein with reference to the signal medium associated therewith. Thus, when used with reference to an electronic device, such as an IC that operates using electrical signals, the term “interconnect” describes any element formed of an electrically conductive material for providing electrical connectivity to one or more elements associated with the IC or/and between various such elements. In such cases, the term “interconnect” may refer to both conductive traces (also sometimes referred to as “lines,” “wires,” “metal lines” or “trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). A conductive via that electrically couples one side of a substrate to an opposite side of the substrate may be referred to herein as a “through-substrate via” or “TSV.” Sometimes, electrically conductive traces and vias may be referred to as “conductive traces” and “conductive vias”, respectively, to highlight the fact that these elements include electrically conductive materials such as metals. Likewise, when used with reference to a device that operates on optical signals as well, such as a PIC, “interconnect” may also describe any element formed of a material that is optically conductive for providing optical connectivity to one or more elements associated with the PIC. In such cases, the term “interconnect” may refer to optical waveguides, including optical fiber, optical splitters, optical combiners, optical couplers, and optical vias.
The term “waveguide” refers to any structure that acts to guide the propagation of light from one location to another location typically through a substrate material such as silicon or glass. In various examples, waveguides can be formed from silicon, doped silicon, silicon nitride, glasses such as silica (e.g., silicon dioxide or SiO2), borosilicate (e.g., 70-80 wt % SiO2, 7-13 wt % of B2O3, 4-8 wt % Na2O or K2O, and 2-8 wt % of Al2O3) and so forth. Waveguides may be formed using various techniques including but not limited to forming waveguides in situ. For example, in some embodiments, waveguides may be formed in situ in glass using low temperature glass-to-glass bonding or by laser direct writing. Waveguides formed in situ may have lower loss characteristics.
The term “conductive trace” may be used to describe an electrically conductive element isolated by an insulating material. Within IC dies, such insulating material includes interlayer low-k dielectric that is provided within the IC die. Within package substrates, and PCBs such insulating material includes organic materials such as Ajinomoto Buildup Film (ABF), polyimides, or epoxy resin. Such conductive lines are typically arranged in several levels, or several layers, of metallization stacks.
The term “conductive via” may be used to describe an electrically conductive element that interconnects two or more conductive lines of different levels of a metallization stack. To that end, a via may be provided substantially perpendicularly to the plane of an IC die/chip or a support structure over which an IC structure is provided and may interconnect two conductive lines in adjacent levels or two conductive lines in non-adjacent levels.
The term “package substrate” may be used to describe any substrate material that facilitates the packaging together of any collection of semiconductor dies and/or other electrical components such as passive electrical components. As used herein, a package substrate may be formed of any material including, but not limited to, insulating materials such as resin impregnated glass fibers (e.g., PCB or Printed Wiring Boards (PWB)), glass, ceramic, silicon, silicon carbide, etc. In addition, as used herein, a package substrate may refer to a substrate that includes buildup layers (e.g., ABF layers).
The term “metallization stack” may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC die/chip and/or a package substrate.
As used herein, the term “pitch” of interconnects refers to a center-to-center distance between adjacent interconnects.
In context of a stack of dies coupled to one another or in context of a die coupled to a package substrate, the term “interconnect” may also refer to, respectively, die-to-die (DTD) interconnects and die-to-package substrate (DTPS) interconnects. DTD interconnects may also be referred to as first-level interconnects (FLI). DTPS interconnects may also be referred to as Second-Level Interconnects (SLI). Although not specifically shown in all of the present illustrations in order to not clutter the drawings, when DTD or DTPS interconnects are described, a surface of a first die may include a first set of conductive contacts, and a surface of a second die or a package substrate may include a second set of conductive contacts. One or more conductive contacts of the first set may then be electrically and mechanically coupled to some of the conductive contacts of the second set by the DTD or DTPS interconnects. In some embodiments, the pitch of the DTD interconnects may be different from the pitch of the DTPS interconnects, although, in other embodiments, these pitches may be substantially the same.
It will be recognized that one more levels of underfill (e.g., organic polymer material such as benzotriazole, imidazole, polyimide, or epoxy) may be provided in an IC package described herein and may not be labeled in order to avoid cluttering the drawings. In various embodiments, the levels of underfill may include the same or different insulating materials. In some embodiments, the levels of underfill may include thermoset epoxies with silicon oxide particles; in some embodiments, the levels of underfill may include any suitable material that can perform underfill functions such as supporting the dies and reducing thermal stress on interconnects. In some embodiments, the choice of underfill material may be based on design considerations, such as form factor, size, stress, operating conditions, etc.; in other embodiments, the choice of underfill material may be based on material properties and processing conditions, such as cure temperature, glass transition temperature, viscosity and chemical resistance, among other factors; in some embodiments, the choice of underfill material may be based on both design and processing considerations.
In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymers, dry film photoimageable polymers, acrylics, solvents) may be provided in an IC package described herein and may not be labeled or shown to avoid cluttering the drawings. Solder resist may be a liquid or dry film material including photoimageable polymers. In some embodiments, solder resist may be non-photoimageable.
The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value (e.g., within +/−5% or 10% of a target value) based on the context of a particular value as described herein or as known in the art.
Terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5%-20% of a target value based on the context of a particular value as described herein or as known in the art.
The term “connected” means a direct connection (which may be one or more of a mechanical, electrical, and/or thermal connection) between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments.
Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments.
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with one or both of the two layers or may have one or more intervening layers. In contrast, a first layer described to be “on” a second layer refers to a layer that is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
The term “dispose” as used herein refers to position, location, placement, and/or arrangement rather than to any particular method of formation.
The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used herein, the notation “A/B/C” means (A), (B), and/or (C).
Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “an electrically conductive material” may include one or more electrically conductive materials. In another example, “a dielectric material” may include one or more dielectric materials.
Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.
The accompanying drawings are not necessarily drawn to scale.
In the drawings, same reference numerals refer to the same or analogous elements/materials shown so that, unless stated otherwise, explanations of an element/material with a given reference numeral provided in context of one of the drawings are applicable to other drawings where element/materials with the same reference numerals may be illustrated. Further, the singular and plural forms of the labels may be used with reference numerals to denote a single one and multiple ones respectively of the same or analogous type, species, or class of element.
Furthermore, in the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using, e.g., images of suitable characterization tools such as scanning electron microscopy (SEM) images, transmission electron microscope (TEM) images, or non-contact profilometer. In such images of real structures, possible processing and/or surface defects could also be visible, e.g., surface roughness, curvature or profile deviation, pit or scratches, not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region(s), and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication and/or packaging.
Note that in the figures, various components (e.g., interconnects) are shown as aligned (e.g., at respective interfaces) merely for ease of illustration; in actuality, some or all of them may be misaligned. In addition, there may be other components, such as bond-pads, landing pads, metallization, etc. present in the assembly that are not shown in the figures to prevent cluttering. Further, the figures are intended to show relative arrangements of the components within their assemblies, and, in general, such assemblies may include other components that are not illustrated (e.g., various interfacial layers or various other components related to optical functionality, electrical connectivity, or thermal mitigation). For example, in some further embodiments, the assembly as shown in the figures may include more dies along with other electrical components. Additionally, although some components of the assemblies are illustrated in the figures as being planar rectangles or formed of rectangular solids, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by and sometimes inevitable due to the manufacturing processes used to fabricate various components.
In the drawings, a particular number and arrangement of structures and components are presented for illustrative purposes and any desired number or arrangement of such structures and components may be present in various embodiments.
Further, unless otherwise specified, the structures shown in the figures may take any suitable form or shape according to material properties, fabrication processes, and operating conditions.
For convenience, if a collection of drawings designated with different letters are present (e.g.,
Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
Metallization stack 102 may be on a substrate 110 (e.g., at an interface 108). Interface 108 may be orthogonal to surface 104 and parallel to surfaces 106 (e.g., in the xy-plane). It is to be understood that while the interface 108 is in the xy-plane, the interface 108 may not be exactly planar. The substrate 110 may further include active region 112. In some embodiments, active region 112 may include transistors, diodes, and other active circuitry and may be proximate to interface 108. In some other embodiments, active region 112 may be absent, or alternatively, transistors, diodes, and other active circuitry may be absent in active region 112. Substrate 110 may have a surface 114 that may be coplanar with surface 104. In some embodiments, substrate 110 may include a semiconductor material as listed above in the previous subsection. In other embodiments, substrate 110 may include glass, ceramic, or other materials that may be suitable for creating functional elements of an IC.
Substrate 110 may further include a conductive via 202 at surface 114, such that a portion of conductive via 202 is exposed on surface 114; such exposed portion may form a bonding portion 124. Conductive via 202 may include a conductive metal, such as copper, in many embodiments. One or more of conductive vias 202 may be exposed on surface 104 as bonding portions 124, as described below with reference to
In various embodiments, metallization stack 102 may include a dielectric material, or a plurality of layers of dielectric material, and conductive pathways (e.g., conductive traces 120 and conductive vias 122) through the dielectric material. The conductive traces 120 may be parallel to surface 106 such that conductive traces 120 are orthogonal to surface 104. In some embodiments, a dielectric material of the metallization stack 102 may include silicon oxide; in other embodiments, the dielectric material of the metallization stack 102 may include any suitable dielectric material used as interlayer dielectrics (ILD) in a typical semiconductor IC die and as described above in the previous subsection. In various embodiments, there may be several conductive traces 120 between interface 108 and surface 106. In some embodiments, there may be between 2 and 6 layers of conductive traces 120 in the plurality of layers of dielectric material. Conductive vias 122 through the dielectric material may conductively connect conductive traces 120 to active circuitry in active region 112 and to conductive via 202. Conductive vias 122 are orthogonal to conductive traces 120. Conductive traces 120 and conductive vias 122 may include a conductive metal, such as copper, in many embodiments.
In many embodiments, IC die 302 may be large-sized, for example, as large as a conventional reticle, which can be approximately 850 square millimeters in footprint area. In various embodiments, IC die 302 may include an interposer with conductive traces to enable conductive coupling of IC die 100 with other IC dies and/or package substrates, and IC die 302 may not have any active circuitry therein. In other embodiments, IC die 302 may include active circuitry. In many embodiments, IC dies 100 may be conductively coupled by conductive pathways in IC die 302. For example, IC die 302 may include a network on chip, interconnecting compute circuitry of IC dies 100 together. The plurality of IC dies 100 may be coupled to IC die 302 by any suitable interconnects, for example, interconnects 352, as shown in
As shown in
In various embodiments, IC dies 100 may be arranged such that a gap 312 exists between adjacent IC dies 100, for example, as shown between IC die 100(1) and 100(2). If microelectronic assembly 300 includes multiple gaps 312, in some embodiments, the multiple gaps 312 may be uniform across microelectronic assembly 300 and may range approximately in the order of a few millimeters (e.g., less than 5 millimeters); in other embodiments, multiple gaps 312 may be non-uniform, with some IC dies 100 being closer to other than other IC dies 100. In some such embodiments, IC dies 100 may include circuitry that consumes electrical power and generates heat during operation. For example, IC dies 100 may include compute circuitry of a microprocessor. Gap 312 may be configured for flow of a cooling fluid therethrough. The cooling fluid (not shown) may be air in some embodiments; in other embodiments, the cooling fluid may be a liquid coolant.
In some embodiments, IC dies 100 may include memory circuitry, and IC die 302 may include a network on chip circuitry, conductively coupling the array of IC dies 100. In some other embodiments, some IC dies 100 may include memory circuitry (e.g., high bandwidth memory (HBM) circuitry) and other IC dies may include compute circuitry and IC die 302 may include a network on chip circuitry. Any suitable configuration of circuitry may be provided in microelectronic assembly 300 among IC dies 100 and IC die 302 as desired and based on particular needs.
The interconnects 352 may also be referred to herein as “DTD interconnects.” The DTD interconnects 352 disclosed herein may take any suitable form. In some embodiments, one side of a DTD interconnect 352 may include a metal bond-pad (e.g., conductive bonding-portion 124 of conductive via 202 of IC die 100), and the other side of the DTD interconnect 352 may include a metal contact (e.g., a conductive contact 125 of IC die 302). In some embodiments, the DTD interconnects 352 may include solder (e.g., solder bumps or balls that are subject to a thermal reflow to form the DTD interconnects 352). DTD interconnects 352 that include solder may include any appropriate solder material, such as lead/tin, tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, tin/nickel/copper, tin/bismuth/copper, tin/indium/copper, tin/zinc/indium/bismuth, or other alloys. For example, the DTD interconnects 352 may include conductive bond-pads (e.g., conductive bonding-portion 124 of IC die 100) attached to the respective conductive contacts (e.g., a conductive contact 125 of IC die 302) by solder.
IC die 302 may include conductive vias 204 and may be coupled to the package substrate 404 by interconnects 353. The interconnects 353 may also be referred to herein as “DTPS interconnects.” The DTPS interconnects 353 disclosed herein may take any suitable form. In some embodiments, a set of DTPS interconnects 353 may include solder (e.g., solder bumps or balls that are subject to a thermal reflow to form the DTPS interconnects 353). DTPS interconnects 353 that include solder may include any appropriate solder material, as described above, with reference to DTD interconnects 352.
In some embodiments, the solder used in some or all of the DTD interconnects 352 may have a higher melting point than the solder included in some or all of the DTPS interconnects 353. For example, when the DTD interconnects 352 in an IC package are formed before the DTPS interconnects 353 are formed, solder-based DTD interconnects 352 may use a higher-temperature solder (e.g., with a melting point above 200 degrees Celsius), while the DTPS interconnects 353 may use a lower-temperature solder (e.g., with a melting point below 200 degrees Celsius). In some embodiments, a higher-temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, a lower-temperature solder may include tin and bismuth (e.g., eutectic tin bismuth), tin, silver, bismuth, indium, indium and tin, or gallium.
In microelectronic assemblies or IC packages as described herein, some or all of the DTD interconnects 352 may have a finer pitch than the DTPS interconnects 353. In some embodiments, the DTPS interconnects 353 disclosed herein may have a pitch between about 80 microns and 300 microns, while the DTD interconnects 352 disclosed herein may have a pitch between about 10 microns and 55 microns. An example of silicon-level interconnect density is provided by the density of some DTD interconnects. In some embodiments, the DTD interconnects 352 may have too fine a pitch to couple to the package substrate directly (e.g., too fine to serve as DTPS interconnects 353). The DTD interconnects 352 may have a smaller pitch than the DTPS interconnects 353 due to the greater similarity of materials in the different dies on either side of a set of DTD interconnects 352 (e.g., IC die 100 and IC die 302) than between a die and a package substrate on either side of a set of DTPS interconnects (e.g., IC die 302 and package substrate 404). In particular, the differences in the material composition of dies and package substrates may result in differential expansion and contraction of the die dies and package substrates due to heat generated during operation (as well as the heat applied during various manufacturing operations). To mitigate damage caused by this differential expansion and contraction (e.g., cracking, solder bridging, etc.), the DTPS interconnects 353 in any of the microelectronic assemblies or IC packages as described herein may be formed larger and farther apart than DTD interconnects 352, which may experience less thermal stress due to the greater material similarity of the pair of dies on either side of the DTD interconnects 352.
In some embodiments, the microelectronic assembly 300 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend between the surfaces 104, 114 of IC dies 100 and the surface 306 of IC die 302 around the associated interconnects 352 and/or between a bottom surface of IC die 302 and a top surface of the package substrate 404 around the associated interconnects 353. The underfill material 127 may be an insulating material, such as an appropriate epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, non-conductive film (NCF), or molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that assists with soldering IC dies 100 to IC die 302 and IC die 302 to the package substrate 404 when forming the interconnects 352, 353, respectively, and then polymerizes and encapsulates the interconnects 352, 353. The underfill material 127 may be selected to have a coefficient of thermal expansion (CTE) that may mitigate or minimize the stress between IC dies 100 and IC die 302, and between IC die 302 and the package substrate 404 arising from uneven thermal expansion in the microelectronic assembly 300. Although
The package substrate 404 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways to route power, ground, and signals through the dielectric material (e.g., including conductive traces and/or conductive vias, as shown). In some embodiments, the insulating material of the package substrate 404 may be a dielectric material, such as an organic dielectric material, a fire retardant grade 4 material (FR-4), BT resin, polyimide materials, glass reinforced epoxy matrix materials, organic dielectrics with inorganic fillers or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In particular, when the package substrate 404 is formed using standard printed circuit board (PCB) processes, the package substrate 404 may include FR-4, and the conductive pathways in the package substrate 404 may be formed by patterned sheets of copper separated by build-up layers of the FR-4. The conductive pathways in the package substrate 404 may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable. In some embodiments, the package substrate 404 may be formed using a lithographically defined via packaging process. In some embodiments, the package substrate 404 may be manufactured using standard organic package manufacturing processes, and thus the package substrate 404 may take the form of an organic package. In some embodiments, the package substrate 404 may be a set of redistribution layers formed on a panel carrier by laminating or spinning on a dielectric material, and creating conductive vias and lines by laser drilling and plating. In some embodiments, the package substrate 404 may be formed on a removable carrier using any suitable technique, such as a redistribution layer technique. Any method known in the art for fabrication of the package substrate 404 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.
In some embodiments, the microelectronic assembly 300 may also include a circuit board (not shown). The package substrate 404 may be coupled to the circuit board by interconnects (not shown) at the bottom surface of the package substrate 404. The interconnects may be any suitable interconnects, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement or lands in a land grid array arrangement. The circuit board may be a motherboard, for example, and may have other components attached to it. The circuit board may include conductive pathways and other conductive contacts for routing power, ground, and signals through the circuit board, as known in the art. In some embodiments, the interconnects may not couple the package substrate 404 to a circuit board, but may instead couple the package substrate 404 to another IC package, an interposer, or any other suitable component.
In various embodiments, any of the features discussed with reference to any of
At 704, the bonding portion 124 of conductive via 202 in IC die 100 (e.g., a first IC die) may be electrically coupled to surface 306 of IC die 302 (e.g., a second IC die) along respective lateral surface 114 (e.g., planarized surface that is orthogonal to surface 106) of IC die 100 with interconnects 352 that include solder. In particular, conductive bonding-portion 124 of conductive via 202 at surface 114 of IC die 100 may be electrically coupled to a conductive contact 125 on surface 106 of IC die 302 by solder. Interconnects 352 may be formed using any suitable technique, for example, thermal compression bonding or mass reflow. In various embodiments, IC die 302 may include an “interposer” IC die, providing conductive pathways between IC die 100 and with a package substrate 404 or other component. In some embodiments, IC die 302 may include a substrate attached to a metallization stack along an interface that is parallel to surface 306. IC die 100 may be one of a plurality of IC dies 100 that may be electrically coupled to surface 306 of IC die 302 by interconnects 352. Further operations may be performed, such as dispensing an underfill material 127 around interconnects 352 or electrically coupling IC die 302 to a package substrate 404 by interconnects 353.
At 804, stack IC dies 100 on first and second surfaces and bond the stacked IC dies 100 together. In some embodiments, IC dies 100 may be stacked on a carrier, bonded together, then removed from the carrier. Lateral surface 104 of IC dies 100 may be planarized before stacking and bonding together, or may be planarized after stacking and bonding together. In some embodiments, wafers including IC dies 100 may be stacked, bonded together, then singulated and planarized.
At 806, conductive bonding-portions 124 at lateral surface 104 of stacked and bonded IC dies 100 (e.g., first IC dies) may be electrically coupled to conductive contacts 125 at surface 306 of IC die 302 (e.g., second IC die) forming interconnects 352. Interconnects 352 may include solder and may be formed using any suitable technique, for example, thermal compression bonding or mass reflow. Operations 802, 804, and 806, as described above, may be repeated to add another layer of IC die 100, except that IC die 100 may be selected from embodiments in
Although
Furthermore, the operations illustrated in
The packages disclosed herein, e.g., any of the embodiments shown in
As shown in the figure, package substrate 2252 may be formed of an insulator (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, etc.), and may have conductive pathways extending through the insulator between first face 2272 and second face 2274, or between different locations on first face 2272, and/or between different locations on second face 2274. These conductive pathways may take the form of any of the interconnect structures comprising lines and/or vias.
Package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathway 2262 through package substrate 2252, allowing circuitry within dies 2256 and/or interposer 2257 to electrically couple to various ones of conductive contacts 2264 (or to other devices included in package substrate 2252, not shown).
IC package 2200 may include interposer 2257 coupled to package substrate 2252 via conductive contacts 2261 of interposer 2257, first-level interconnects 2265, and conductive contacts 2263 of package substrate 2252. First-level interconnects 2265 illustrated in the figure are solder bumps, but any suitable first-level interconnects 2265 may be used, such as solder bumps, solder posts, or bond wires.
IC package 2200 may include one or more dies 2256 coupled to interposer 2257 via conductive contacts 2254 of dies 2256, first-level interconnects 2258, and conductive contacts 2260 of interposer 2257. Conductive contacts 2260 may be coupled to conductive pathways (not shown) through interposer 2257, allowing circuitry within dies 2256 to electrically couple to various ones of conductive contacts 2261 (or to other devices included in interposer 2257, not shown). First-level interconnects 2258 illustrated in the figure are solder bumps, but any suitable first-level interconnects 2258 may be used, such as solder bumps, solder posts, or bond wires. As used herein, a “conductive contact” may refer to a portion of electrically conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).
In some embodiments, underfill material 2266 may be disposed between package substrate 2252 and interposer 2257 around first-level interconnects 2265, and mold 2268 may be disposed around dies 2256 and interposer 2257 and in contact with package substrate 2252. In some embodiments, underfill material 2266 may be the same as mold 2268. Example materials that may be used for underfill material 2266 and mold 2268 are epoxies as suitable. Second-level interconnects 2270 may be coupled to conductive contacts 2264. Second-level interconnects 2270 illustrated in the figure are solder balls (e.g., for a ball grid array (BGA) arrangement), but any suitable second-level interconnects 2270 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). Second-level interconnects 2270 may be used to couple IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to
In various embodiments, any of dies 2256 may be microelectronic assembly 300 as described herein. In embodiments in which IC package 2200 includes multiple dies 2256, IC package 2200 may be referred to as a multi-chip package (MCP). Dies 2256 may include circuitry to perform any desired functionality. For example, besides one or more of dies 2256 being microelectronic assembly 300 as described herein, one or more of dies 2256 may be logic dies (e.g., silicon-based dies), one or more of dies 2256 may be memory dies (e.g., HBM), etc. In some embodiments, any of dies 2256 may be implemented as discussed with reference to any of the previous figures. In some embodiments, at least some of dies 2256 may not include implementations as described herein.
Although IC package 2200 illustrated in the figure is a flip-chip package, other package architectures may be used. For example, IC package 2200 may be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, IC package 2200 may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are illustrated in IC package 2200, IC package 2200 may include any desired number of dies 2256. IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed over first face 2272 or second face 2274 of package substrate 2252, or on either face of interposer 2257. More generally, IC package 2200 may include any other active or passive components known in the art.
In some embodiments, no interposer 2257 may be included in IC package 2200; instead, dies 2256 may be coupled directly to conductive contacts 2263 at first face 2272 by first-level interconnects 2265.
In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from one another by layers of insulator and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to circuit board 2302. In other embodiments, circuit board 2302 may be a non-PCB package substrate.
As illustrated in the figure, in some embodiments, IC device assembly 2300 may include a package-on-interposer structure 2336 coupled to first face 2340 of circuit board 2302 by coupling components 2316. Coupling components 2316 may electrically and mechanically couple package-on-interposer structure 2336 to circuit board 2302, and may include solder balls (as shown), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
Package-on-interposer structure 2336 may include IC package 2320 coupled to interposer 2304 by coupling components 2318. Coupling components 2318 may take any suitable form depending on desired functionalities, such as the forms discussed above with reference to coupling components 2316. In some embodiments, IC package 2320 may be or include IC package 2200, e.g., as described above with reference to
Although a single IC package 2320 is shown in the figure, multiple IC packages may be coupled to interposer 2304; indeed, additional interposers may be coupled to interposer 2304. Interposer 2304 may provide an intervening package substrate used to bridge circuit board 2302 and IC package 2320. Generally, interposer 2304 may redistribute a connection to a wider pitch or reroute a connection to a different connection. For example, interposer 2304 may couple IC package 2320 to a BGA of coupling components 2316 for coupling to circuit board 2302.
In the embodiment illustrated in the figure, IC package 2320 and circuit board 2302 are attached to opposing sides of interposer 2304. In other embodiments, IC package 2320 and circuit board 2302 may be attached to a same side of interposer 2304. In some embodiments, three or more components may be interconnected by way of interposer 2304.
Interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. Interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. Interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on interposer 2304. Package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.
In some embodiments, IC device assembly 2300 may include an IC package 2324 coupled to first face 2340 of circuit board 2302 by coupling components 2322. Coupling components 2322 may take the form of any of the embodiments discussed above with reference to coupling components 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.
In some embodiments, IC device assembly 2300 may include a package-on-package structure 2334 coupled to second face 2342 of circuit board 2302 by coupling components 2328. Package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together by coupling components 2330 such that IC package 2326 is disposed between circuit board 2302 and IC package 2332. Coupling components 2328 and 2330 may take the form of any of the embodiments of coupling components 2316 discussed above, and IC packages 2326 and/or 2332 may take the form of any of the embodiments of IC package 2320 discussed above. Package-on-package structure 2334 may be configured in accordance with any of the package-on-package structures known in the art.
A number of components are illustrated in the figure as included in computing device 2400, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-chip (SOC) die.
Additionally, in various embodiments, computing device 2400 may not include one or more of the components illustrated in the figure, but computing device 2400 may include interface circuitry for coupling to the one or more components. For example, computing device 2400 may not include a display device 2406, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which display device 2406 may be coupled. In another set of examples, computing device 2400 may not include an audio input device 2418 or an audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which audio input device 2418 or audio output device 2408 may be coupled.
Computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. Computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive. In some embodiments, memory 2404 may include memory that shares a die with processing device 2402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some embodiments, computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured for managing wireless communications for the transfer of data to and from computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
Communication chip 2412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), LTE project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 2412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Communication chip 2412 may operate in accordance with other wireless protocols in other embodiments. Computing device 2400 may include an antenna 2422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, communication chip 2412 may include multiple communication chips. For instance, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communications, and a second communication chip 2412 may be dedicated to wired communications.
Computing device 2400 may include battery/power circuitry 2414. Battery/power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of computing device 2400 to an energy source separate from computing device 2400 (e.g., AC line power).
Computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above). Display device 2406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
Computing device 2400 may include audio output device 2408 (or corresponding interface circuitry, as discussed above). Audio output device 2408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
Computing device 2400 may include audio input device 2418 (or corresponding interface circuitry, as discussed above). Audio input device 2418 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
Computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). GPS device 2416 may be in communication with a satellite-based system and may receive a location of computing device 2400, as known in the art.
Computing device 2400 may include other output device 2410 (or corresponding interface circuitry, as discussed above). Examples of other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
Computing device 2400 may include other input device 2420 (or corresponding interface circuitry, as discussed above). Examples of other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
Computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, computing device 2400 may be any other electronic device that processes data.
The descriptions of illustrated implementations of the disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 is a microelectronic assembly, including a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a trace that is parallel to the first and second surfaces, and a via having a portion exposed at the third surface, wherein the trace and the via include a conductive material; and a second IC die having a fourth surface with a conductive contact, the second IC die electrically coupled to the first IC die by an interconnect, wherein the interconnect includes the portion of the via exposed at the third surface of the first IC die electrically coupled by solder to the conductive contact at the fourth surface of the second IC die.
Example 2 may include the subject matter of Example 1, and may further specify that the first IC die is one of a plurality of first IC dies.
Example 3 may include the subject matter of Example 2, and may further specify that the plurality of first IC dies are spaced apart from each other by a gap.
Example 4 may include the subject matter of Example 2, and may further specify that the plurality of first IC dies are bonded together at respective first and second surfaces.
Example 5 may include the subject matter of Example 4, and may further specify that the plurality of first IC dies are bonded together by oxide-oxide bonds.
Example 6 may include the subject matter of any of Examples 1-5, and may further specify that the second IC die further includes a fifth surface opposite the fourth surface, and the microelectronic assembly may further include a package substrate electrically coupled to the fifth surface of the second IC die.
Example 7 may include the subject matter of any of Examples 1-6, and may further specify that the first IC die further includes a substrate and a metallization stack having an interface that is parallel to the first and second surfaces.
Example 8 may include the subject matter of any of Examples 1-7, and may further specify that the portion of the via exposed at the third surface is a first portion of a first via, and wherein the first IC die further includes a sixth surface opposite the third surface, the sixth surface having a second portion of a second via exposed at the sixth surface.
Example 9 may include the subject matter of Example 8, and may further specify that the first IC die is one of a plurality of first IC die in a first layer, and the microelectronic assembly may further include a plurality of first IC die in a second layer on the first layer of first IC die, wherein the second portions of the second vias in the plurality of first IC dies in the first layer are electrically coupled by interconnects to the first portions of the first vias in the plurality of first IC dies in the second layer, and wherein the interconnects include solder.
Example 10 is a microelectronic assembly, including a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a substrate and a metallization stack having an interface that is parallel to the first and second surfaces, and the substrate including a conductive via having a portion exposed at the third surface; and a second IC die including a fourth surface, wherein the portion of the conductive via exposed at the third surface of the first IC die is electrically coupled to the fourth surface of the second IC die by an interconnect including solder.
Example 11 may include the subject matter of Example 10, and may further specify that the first IC die is one of a plurality of first IC dies.
Example 12 may include the subject matter of Example 11, and may further specify that the plurality of first IC dies are bonded together on respective first and second surfaces.
Example 13 may include the subject matter of Example 12, and may further specify that the plurality of first IC dies are bonded together by oxide-oxide bonds.
Example 14 may include the subject matter of any of Examples 10-13, and may further specify that the first IC die further includes conductive pathways electrically coupled to the conductive via and the conductive pathways include conductive traces that are parallel to the first and second surfaces.
Example 15 may include the subject matter of any of Examples 10-14, and may further specify that the portion of the conductive via exposed at the third surface is a first portion of a first conductive via, and wherein the first IC die further includes a sixth surface opposite the third surface, the sixth surface having a second portion of a second conductive via exposed at the sixth surface.
Example 16 may include the subject matter of Example 15, and may further specify that the first IC die is one of a plurality of first IC die in a first layer, and the microelectronic assembly may further include a plurality of first IC die in a second layer on the first layer of first IC die, wherein the second portions of the second conductive vias in the plurality of first IC dies in the first layer are electrically coupled by interconnects to the first portions of the first conductive vias in the plurality of first IC dies in the second layer, and wherein the interconnects include solder.
Example 17 is a microelectronic assembly, including a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive via having a portion exposed at the third surface and a conductive pathway electrically coupled to the conductive via, wherein the conductive pathway includes a conductive trace that is parallel to the first and second surfaces; a second IC die including a fourth surface and a fifth surface opposite the fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the portion of the conductive via exposed at the third surface of the first IC die by first interconnects including solder; and a package substrate electrically coupled to the fifth surface of the second IC die by second interconnects.
Example 18 may include the subject matter of Example 17, and may further specify that the first IC die is one of a plurality of first IC dies.
Example 19 may include the subject matter of Examples 17 or 18, and may further specify that the first IC die further includes a substrate and a metallization stack having an interface that is parallel to the first and second surfaces.
Example 20 may include the subject matter of Example 19, and may further specify that the first IC die further includes memory circuitry.
