Qi Xiang

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
High yield package assembly technique
- Patent number 10,707,138
- Issue date Jul 7, 2020
- Xilinx, Inc.
- Shiying Xiong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits with asymmetric and stacked transistors
- Patent number 9,496,268
- Issue date Nov 15, 2016
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element circuitry with minimum oxide definition width
- Patent number 9,461,161
- Issue date Oct 4, 2016
- Altera Corporation
- Jun Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having structure with fractional dimension of...
- Patent number 9,460,924
- Issue date Oct 4, 2016
- GLOBALFOUNDRIES, INC.
- Witold P. Maszara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Charge damage protection on an interposer for a stacked die assembly
- Patent number 9,214,433
- Issue date Dec 15, 2015
- Xilinx, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable device with a metal oxide semiconductor field effect t...
- Patent number 9,196,749
- Issue date Nov 24, 2015
- Altera Corporation
- Charu Sardana
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating integrated circuit transistors with multipart...
- Patent number 9,190,332
- Issue date Nov 17, 2015
- Altera Corporation
- Jun Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of using a PMOS pass gate
- Patent number 9,165,640
- Issue date Oct 20, 2015
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross-coupling based design using diffusion contact structures
- Patent number 8,987,128
- Issue date Mar 24, 2015
- GLOBALFOUNDRIES Inc.
- Mahbub Rashed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating optimal planar and three-dimensional semiconductor desi...
- Patent number 8,966,423
- Issue date Feb 24, 2015
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parameterized cell for planar and finFET technology design
- Patent number 8,904,324
- Issue date Dec 2, 2014
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PMOS pass gate
- Patent number 8,804,407
- Issue date Aug 12, 2014
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuits with asymmetric and stacked transistors
- Patent number 8,750,026
- Issue date Jun 10, 2014
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit transistors with multipart gate conductors
- Patent number 8,735,983
- Issue date May 27, 2014
- Altera Corporation
- Jun Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits and methods for fabricating integrated circuits...
- Patent number 8,735,050
- Issue date May 27, 2014
- GLOBALFOUNDRIES, INC.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory element circuitry with reduced oxide definition width
- Patent number 8,649,209
- Issue date Feb 11, 2014
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable integrated circuit with thin-oxide passgates
- Patent number 8,633,731
- Issue date Jan 21, 2014
- Altera Corporation
- Irfan Rahim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element transistors with reversed-workfunction gate conductors
- Patent number 8,530,976
- Issue date Sep 10, 2013
- Altera Corporation
- Albert Ratnakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained fully depleted silicon on insulator semiconductor device
- Patent number 8,502,283
- Issue date Aug 6, 2013
- GLOBALFOUNDRIES Inc.
- Qi Xiang
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Integrated circuits with asymmetric and stacked transistors
- Patent number 8,482,963
- Issue date Jul 9, 2013
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Very low voltage reference circuit
- Patent number 8,264,214
- Issue date Sep 11, 2012
- Altera Corporation
- Albert Ratnakumar
- G05 - CONTROLLING REGULATING
Information Patent Grant
Mixed-gate metal-oxide-semiconductor varactors
- Patent number 8,242,581
- Issue date Aug 14, 2012
- Altera Corporation
- Albert Ratnakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory element circuitry with stressed transistors
- Patent number 8,218,353
- Issue date Jul 10, 2012
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Stressed transistors with reduced leakage
- Patent number 8,138,791
- Issue date Mar 20, 2012
- Altera Corporation
- Albert Ratnakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory elements with body bias control
- Patent number 8,081,502
- Issue date Dec 20, 2011
- Altera Corporation
- Irfan Rahim
- G11 - INFORMATION STORAGE
Information Patent Grant
Process/design methodology to enable high performance logic and ana...
- Patent number 7,952,423
- Issue date May 31, 2011
- Altera Corporation
- Qi Xiang
- G05 - CONTROLLING REGULATING
Information Patent Grant
Field effect transistor having increased carrier mobility
- Patent number 7,923,785
- Issue date Apr 12, 2011
- GLOBALFOUNDRIES Inc.
- Qi Xiang
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Shallow trench isolation process and structure with minimized strai...
- Patent number 7,732,336
- Issue date Jun 8, 2010
- GLOBALFOUNDRIES Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming isolation regions for integrated circuits
- Patent number 7,713,834
- Issue date May 11, 2010
- GLOBALFOUNDRIES Inc.
- Haihong Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation process
- Patent number 7,648,886
- Issue date Jan 19, 2010
- GLOBALFOUNDRIES Inc.
- Minh-Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Integrated Circuits with Asymmetric and Stacked Transistors
- Publication number 20160232952
- Publication date Aug 11, 2016
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuits with Asymmetric and Stacked Transistors
- Publication number 20150318029
- Publication date Nov 5, 2015
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Application
CHARGE DAMAGE PROTECTION ON AN INTERPOSER FOR A STACKED DIE ASSEMBLY
- Publication number 20140346651
- Publication date Nov 27, 2014
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN
- Publication number 20140282323
- Publication date Sep 18, 2014
- GLOBALFOUNDRIES INC.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESI...
- Publication number 20140258960
- Publication date Sep 11, 2014
- GLOBALFOUNDRIES INC.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS...
- Publication number 20140035151
- Publication date Feb 6, 2014
- GLOBALFOUNDRIES INC.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS-COUPLING BASED DESIGN USING DIFFUSION CONTACT STRUCTURES
- Publication number 20140027918
- Publication date Jan 30, 2014
- GLOBALFOUNDRIES INC.
- Mahbub Rashed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERY LOW VOLTAGE REFERENCE CIRCUIT
- Publication number 20120235662
- Publication date Sep 20, 2012
- Albert Ratnakumar
- G05 - CONTROLLING REGULATING
Information Patent Application
ASYMMETRIC METAL-OXIDE-SEMICONDUCTOR TRANSISTORS
- Publication number 20100127331
- Publication date May 27, 2010
- Albert Ratnakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT TRANSISTORS
- Publication number 20100127332
- Publication date May 27, 2010
- Jun Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS/DESIGN METHODOLOGY TO ENABLE HIGH PERFORMANCE LOGIC AND ANA...
- Publication number 20100079200
- Publication date Apr 1, 2010
- Qi Xiang
- G05 - CONTROLLING REGULATING
Information Patent Application
VARACTORS WITH ENHANCED TUNING RANGES
- Publication number 20100019351
- Publication date Jan 28, 2010
- Albert Ratnakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS
- Publication number 20090047770
- Publication date Feb 19, 2009
- Advanced Micro Devices, Inc.
- Haihong Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING STRUCTURE WITH FRACTIONAL DIMENSION OF...
- Publication number 20080237803
- Publication date Oct 2, 2008
- Advanced Micro Devices, Inc.
- Witold P. Maszara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE WITH MINIMIZED STRAI...
- Publication number 20080213952
- Publication date Sep 4, 2008
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED FULLY DEPLETED SILICON ON INSULATOR SEMICONDUCTOR DEVICE
- Publication number 20080054316
- Publication date Mar 6, 2008
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor on insulator substrate and devices formed therefrom
- Publication number 20060138542
- Publication date Jun 29, 2006
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Strained fully depleted silicon on insulator semiconductor device a...
- Publication number 20060099752
- Publication date May 11, 2006
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor on insulator substrate and devices formed therefrom
- Publication number 20050224879
- Publication date Oct 13, 2005
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a strained silicon channel FinFET
- Publication number 20050153486
- Publication date Jul 14, 2005
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Shallow trench isolation process and structure with minimized strai...
- Publication number 20050151222
- Publication date Jul 14, 2005
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with two phase fuse material and method of using...
- Publication number 20050124097
- Publication date Jun 9, 2005
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for integrating a high-k gate dielectric in a transistor fab...
- Publication number 20050101147
- Publication date May 12, 2005
- Advanced Micro Devices, Inc.
- Catherine B. Labelle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicon buffered shallow trench isolation for strained silicon proc...
- Publication number 20050095807
- Publication date May 5, 2005
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Shallow trench isolation (STI) region with high-K liner and method...
- Publication number 20050073022
- Publication date Apr 7, 2005
- Olov B. Karlsson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR INTEGRATING METALS HAVING DIFFERENT WORK FUNCTIONS TO FO...
- Publication number 20050054149
- Publication date Mar 10, 2005
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Strained silicon MOSFETs having reduced diffusion of n-type dopants
- Publication number 20050054164
- Publication date Mar 10, 2005
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of growing as a channel region to reduce source/drain juncti...
- Publication number 20050048743
- Publication date Mar 3, 2005
- Advanced Micro Devices, Inc.
- Ihsan J. Djomehri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF FINFET USING A SIDEWALL EPITAXIAL LAYER
- Publication number 20050048727
- Publication date Mar 3, 2005
- Advanced Micro Devices, Inc.
- Witold P. Maszara
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
Field effect transistor having increased carrier mobility
- Publication number 20050040477
- Publication date Feb 24, 2005
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

High yield package assembly technique

Integrated circuits with asymmetric and stacked transistors

Memory element circuitry with minimum oxide definition width

Semiconductor device having structure with fractional dimension of...

Charge damage protection on an interposer for a stacked die assembly

Programmable device with a metal oxide semiconductor field effect t...

Method of fabricating integrated circuit transistors with multipart...

Method of using a PMOS pass gate

Cross-coupling based design using diffusion contact structures

Integrating optimal planar and three-dimensional semiconductor desi...

Parameterized cell for planar and finFET technology design

PMOS pass gate

Integrated circuits with asymmetric and stacked transistors

Integrated circuit transistors with multipart gate conductors

Integrated circuits and methods for fabricating integrated circuits...

Memory element circuitry with reduced oxide definition width

Programmable integrated circuit with thin-oxide passgates

Memory element transistors with reversed-workfunction gate conductors

Strained fully depleted silicon on insulator semiconductor device

Integrated circuits with asymmetric and stacked transistors

Very low voltage reference circuit

Mixed-gate metal-oxide-semiconductor varactors

Memory element circuitry with stressed transistors

Stressed transistors with reduced leakage

Memory elements with body bias control

Process/design methodology to enable high performance logic and ana...

Field effect transistor having increased carrier mobility

Shallow trench isolation process and structure with minimized strai...

Method of forming isolation regions for integrated circuits

Shallow trench isolation process

Patents Applicationslast 30 patents

Integrated Circuits with Asymmetric and Stacked Transistors

Integrated Circuits with Asymmetric and Stacked Transistors

CHARGE DAMAGE PROTECTION ON AN INTERPOSER FOR A STACKED DIE ASSEMBLY

PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN

INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESI...

INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS...

CROSS-COUPLING BASED DESIGN USING DIFFUSION CONTACT STRUCTURES

VERY LOW VOLTAGE REFERENCE CIRCUIT

ASYMMETRIC METAL-OXIDE-SEMICONDUCTOR TRANSISTORS

INTEGRATED CIRCUIT TRANSISTORS

PROCESS/DESIGN METHODOLOGY TO ENABLE HIGH PERFORMANCE LOGIC AND ANA...

VARACTORS WITH ENHANCED TUNING RANGES

METHOD OF FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS

SEMICONDUCTOR DEVICE HAVING STRUCTURE WITH FRACTIONAL DIMENSION OF...

SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE WITH MINIMIZED STRAI...

STRAINED FULLY DEPLETED SILICON ON INSULATOR SEMICONDUCTOR DEVICE

Semiconductor on insulator substrate and devices formed therefrom

Strained fully depleted silicon on insulator semiconductor device a...

Semiconductor on insulator substrate and devices formed therefrom

Method of fabricating a strained silicon channel FinFET

Shallow trench isolation process and structure with minimized strai...

Integrated circuit with two phase fuse material and method of using...

Method for integrating a high-k gate dielectric in a transistor fab...

Silicon buffered shallow trench isolation for strained silicon proc...

Shallow trench isolation (STI) region with high-K liner and method...

METHOD FOR INTEGRATING METALS HAVING DIFFERENT WORK FUNCTIONS TO FO...

Strained silicon MOSFETs having reduced diffusion of n-type dopants

Method of growing as a channel region to reduce source/drain juncti...

FORMATION OF FINFET USING A SIDEWALL EPITAXIAL LAYER

Field effect transistor having increased carrier mobility