Qinglei Zhang

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 12,132,002
- Issue date Oct 29, 2024
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 11,694,960
- Issue date Jul 4, 2023
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 11,133,257
- Issue date Sep 28, 2021
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package substrate
- Patent number 10,770,387
- Issue date Sep 8, 2020
- Intel Corporation
- Qinglei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 10,475,745
- Issue date Nov 12, 2019
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package substrate
- Patent number 10,325,843
- Issue date Jun 18, 2019
- Intel Corporation
- Qinglei Zhang
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 10,103,103
- Issue date Oct 16, 2018
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package substrate
- Patent number 9,831,169
- Issue date Nov 28, 2017
- Intel Corporation
- Qinglei Zhang
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Low z-height package assembly
- Patent number 9,735,120
- Issue date Aug 15, 2017
- Intel Corporation
- Qinglei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 9,640,485
- Issue date May 2, 2017
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package substrate
- Patent number 9,508,636
- Issue date Nov 29, 2016
- Intel Corporation
- Qinglei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Coreless substrate with passive device pads
- Patent number 9,502,336
- Issue date Nov 22, 2016
- Intel Corporation
- Qinglei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming substrate microvias with anchor structures
- Patent number 9,449,923
- Issue date Sep 20, 2016
- Intel Corporation
- Sri Ranga Sai Boyapati
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Enabling package-on-package (PoP) pad surface finishes on bumpless...
- Patent number 9,299,602
- Issue date Mar 29, 2016
- Intel Corporation
- Qinglei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods of forming substrate microvias with anchor structures
- Patent number 9,245,795
- Issue date Jan 26, 2016
- Intel Corporation
- Sri Ranga Sai Boyapati
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laser cavity formation for embedded dies or components in substrate...
- Patent number 9,202,803
- Issue date Dec 1, 2015
- Intel Corporation
- Chong Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enabling package-on-package (PoP) pad surface finishes on bumpless...
- Patent number 9,190,315
- Issue date Nov 17, 2015
- Intel Corporation
- Qinglei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 9,147,663
- Issue date Sep 29, 2015
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structures for embedded bridge
- Patent number 9,147,638
- Issue date Sep 29, 2015
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20240014138
- Publication date Jan 11, 2024
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20210384129
- Publication date Dec 9, 2021
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20200043852
- Publication date Feb 6, 2020
- Intel Corporation
- Yueli Liu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SUBSTRATE
- Publication number 20190304892
- Publication date Oct 3, 2019
- Intel Corporation
- Qinglei ZHANG
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20190013271
- Publication date Jan 10, 2019
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SUBSTRATE
- Publication number 20180138118
- Publication date May 17, 2018
- Intel Corporation
- Qinglei ZHANG
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20170207168
- Publication date Jul 20, 2017
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SUBSTRATE
- Publication number 20160379923
- Publication date Dec 29, 2016
- Intel Corporation
- Qinglei ZHANG
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
METHODS OF FORMING SUBSTRATE MICROVIAS WITH ANCHOR STRUCTURES
- Publication number 20160104679
- Publication date Apr 14, 2016
- Intel Corporation
- Sri Ranga Sai Boyapati
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20150364423
- Publication date Dec 17, 2015
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SUBSTRATE
- Publication number 20150318236
- Publication date Nov 5, 2015
- Qinglei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LASER CAVITY FORMATION FOR EMBEDDED DIES OR COMPONENTS IN SUBSTRATE...
- Publication number 20150279817
- Publication date Oct 1, 2015
- Chong ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW Z-HEIGHT PACKAGE ASSEMBLY
- Publication number 20150179593
- Publication date Jun 25, 2015
- Qinglei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT STRUCTURES FOR EMBEDDED BRIDGE
- Publication number 20150028486
- Publication date Jan 29, 2015
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of forming dual sided coreless package structures with land...
- Publication number 20140376195
- Publication date Dec 25, 2014
- Qinglei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20140353827
- Publication date Dec 4, 2014
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING SUBSTRATE MICROVIAS WITH ANCHOR STRUCTURES
- Publication number 20140353831
- Publication date Dec 4, 2014
- Sri Ranga Sai BOYAPATI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SUBSTRATE
- Publication number 20140321087
- Publication date Oct 30, 2014
- Qinglei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CORELESS SUBSTRATE WITH PASSIVE DEVICE PADS
- Publication number 20140268612
- Publication date Sep 18, 2014
- Qinglei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENABLING PACKAGE-ON-PACKAGE (POP) PAD SURFACE FINISHES ON BUMPLESS...
- Publication number 20130320547
- Publication date Dec 5, 2013
- Qinglei Zhang
- H01 - BASIC ELECTRIC ELEMENTS

Qinglei Zhang

Person

Patents Grantslast 30 patents

Bridge interconnection with layered interconnect structures

Bridge interconnection with layered interconnect structures

Bridge interconnection with layered interconnect structures

Integrated circuit package substrate

Bridge interconnection with layered interconnect structures

Integrated circuit package substrate

Bridge interconnection with layered interconnect structures

Integrated circuit package substrate

Low z-height package assembly

Bridge interconnection with layered interconnect structures

Integrated circuit package substrate

Coreless substrate with passive device pads

Methods of forming substrate microvias with anchor structures

Enabling package-on-package (PoP) pad surface finishes on bumpless...

Methods of forming substrate microvias with anchor structures

Laser cavity formation for embedded dies or components in substrate...

Enabling package-on-package (PoP) pad surface finishes on bumpless...

Bridge interconnection with layered interconnect structures

Interconnect structures for embedded bridge

Patents Applicationslast 30 patents

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

INTEGRATED CIRCUIT PACKAGE SUBSTRATE

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

INTEGRATED CIRCUIT PACKAGE SUBSTRATE

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

INTEGRATED CIRCUIT PACKAGE SUBSTRATE

METHODS OF FORMING SUBSTRATE MICROVIAS WITH ANCHOR STRUCTURES

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

INTEGRATED CIRCUIT PACKAGE SUBSTRATE

LASER CAVITY FORMATION FOR EMBEDDED DIES OR COMPONENTS IN SUBSTRATE...

LOW Z-HEIGHT PACKAGE ASSEMBLY

INTERCONNECT STRUCTURES FOR EMBEDDED BRIDGE

Methods of forming dual sided coreless package structures with land...

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

METHODS OF FORMING SUBSTRATE MICROVIAS WITH ANCHOR STRUCTURES

INTEGRATED CIRCUIT PACKAGE SUBSTRATE

CORELESS SUBSTRATE WITH PASSIVE DEVICE PADS

ENABLING PACKAGE-ON-PACKAGE (POP) PAD SURFACE FINISHES ON BUMPLESS...