Qwai H. Low

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
3D-interconnect
- Patent number 11,929,337
- Issue date Mar 12, 2024
- Invensas LLC
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D-interconnect
- Patent number 11,031,362
- Issue date Jun 8, 2021
- Invensas Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D-interconnect
- Patent number 10,181,447
- Issue date Jan 15, 2019
- Invensas Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low cost hybrid high density package
- Patent number 9,875,955
- Issue date Jan 23, 2018
- Tessera, Inc.
- Kishor Desai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low cost hybrid high density package
- Patent number 9,508,687
- Issue date Nov 29, 2016
- Tessera, Inc.
- Kishor Desai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low cost hybrid high density package
- Patent number 8,963,310
- Issue date Feb 24, 2015
- Tessera, Inc.
- Kishor Desai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing an electronic device package
- Patent number 8,869,389
- Issue date Oct 28, 2014
- LSI Corporation
- Larry Golick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Area array quad flat no-lead (QFN) package
- Patent number 8,525,312
- Issue date Sep 3, 2013
- Tessera, Inc.
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip-chip QFN structure using etched lead frame
- Patent number 8,525,309
- Issue date Sep 3, 2013
- Tessera, Inc.
- Chok Chia
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Electronic device package and method of manufacture
- Patent number 8,384,205
- Issue date Feb 26, 2013
- LSI Corporation
- Qwai Low
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Package with power and ground through via
- Patent number 8,350,379
- Issue date Jan 8, 2013
- LSI Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead frame design to improve reliability
- Patent number 8,334,467
- Issue date Dec 18, 2012
- LSI Corporation
- Larry W. Golick
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Heat dissipation for integrated circuit
- Patent number 8,134,232
- Issue date Mar 13, 2012
- LSI Corporation
- Mitchel E. Lohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire bonding over active circuits
- Patent number 8,125,091
- Issue date Feb 28, 2012
- LSI Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device package and method of manufacture
- Patent number 7,993,981
- Issue date Aug 9, 2011
- LSI Corporation
- Qwai Low
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Eliminate IMC cracking in post wirebonded dies: macro level stress...
- Patent number 7,531,442
- Issue date May 12, 2009
- LSI Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heat spreader in integrated circuit package
- Patent number 7,420,809
- Issue date Sep 2, 2008
- LSI Corporation
- Hong T. Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated heatspreader for use in wire bonded ball grid array semi...
- Patent number 7,235,889
- Issue date Jun 26, 2007
- LSI Corporation
- Maurice O. Othieno
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure for detecting bonding-induced cracks
- Patent number 6,998,638
- Issue date Feb 14, 2006
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric stack
- Patent number 6,963,138
- Issue date Nov 8, 2005
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure
- Patent number 6,861,748
- Issue date Mar 1, 2005
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer metal layer
- Patent number 6,861,343
- Issue date Mar 1, 2005
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Slotted bonding pad
- Patent number 6,825,563
- Issue date Nov 30, 2004
- LSI Logic Corporation
- Ramaswamy Ranganathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding pad for low k dielectric
- Patent number 6,798,035
- Issue date Sep 28, 2004
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure for detecting bonding-induced cracks
- Patent number 6,781,150
- Issue date Aug 24, 2004
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding pad isolation
- Patent number 6,743,979
- Issue date Jun 1, 2004
- LSI Logic Corporation
- Michael J. Berman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package
- Patent number 6,603,200
- Issue date Aug 5, 2003
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having dedicated probe pads for use in testing d...
- Patent number 6,573,113
- Issue date Jun 3, 2003
- LSI Logic Corporation
- Qwai H. Low
- G01 - MEASURING TESTING
Information Patent Grant
Molded tape ball grid array package
- Patent number 6,489,571
- Issue date Dec 3, 2002
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tape design to reduce warpage
- Patent number 6,486,002
- Issue date Nov 26, 2002
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
3D-INTERCONNECT
- Publication number 20250015031
- Publication date Jan 9, 2025
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3d-Interconnect
- Publication number 20210366857
- Publication date Nov 25, 2021
- Invensas Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D-Interconnect
- Publication number 20190148324
- Publication date May 16, 2019
- Invensas Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D-INTERCONNECT
- Publication number 20180308813
- Publication date Oct 25, 2018
- Invensas Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low cost hybrid high density package
- Publication number 20170077018
- Publication date Mar 16, 2017
- Tessera, Inc.
- Kishor Desai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST HYBRID HIGH DENSITY PACKAGE
- Publication number 20150171058
- Publication date Jun 18, 2015
- Tessera, Inc.
- Kishor Desai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD FRAME DESIGN TO IMPROVE RELIABILITY
- Publication number 20130067743
- Publication date Mar 21, 2013
- LSI Corporation
- Larry Golick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST HYBRID HIGH DENSITY PACKAGE
- Publication number 20130049179
- Publication date Feb 28, 2013
- Tessera, Inc.
- Kishor Desai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AREA ARRAY QFN
- Publication number 20130037925
- Publication date Feb 14, 2013
- Tessera, Inc.
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP-CHIP QFN STRUCTURE USING ETCHED LEAD FRAME
- Publication number 20130001757
- Publication date Jan 3, 2013
- Tessera. Inc.
- Chok Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME USING ABLATION
- Publication number 20120018901
- Publication date Jan 26, 2012
- LSI Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE
- Publication number 20110260324
- Publication date Oct 27, 2011
- LSI Corporation
- Qwai Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD FRAME DESIGN TO IMPROVE RELIABILITY
- Publication number 20100319987
- Publication date Dec 23, 2010
- LSI Corporation
- Larry W. Golick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE
- Publication number 20100314747
- Publication date Dec 16, 2010
- LSI Corporation
- Qwai Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Package with Power and Ground Through Via
- Publication number 20100059865
- Publication date Mar 11, 2010
- LSI Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Heat Dissipation For Integrated Circuit
- Publication number 20090250805
- Publication date Oct 8, 2009
- LSI Corporation
- Mitchel E. Lohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WIRE BONDING OVER ACTIVE CIRCUITS
- Publication number 20090236742
- Publication date Sep 24, 2009
- LSI Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Eliminate IMC cracking in post wirebonded dies: macro level stress...
- Publication number 20070123024
- Publication date May 31, 2007
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bond pad structure for gold wire bonding to copper low K dielectric...
- Publication number 20060113667
- Publication date Jun 1, 2006
- Chok Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated heatspreader for use in wire bonded ball grid array semi...
- Publication number 20060055029
- Publication date Mar 16, 2006
- LSI Logic Corporation
- Maurice O. Othieno
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Heat spreader in integrated circuit package
- Publication number 20050281011
- Publication date Dec 22, 2005
- Hong T. Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Test structure for detecting bonding-induced cracks
- Publication number 20040217487
- Publication date Nov 4, 2004
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wire bonding to full array bonding pads on active circuitry
- Publication number 20040178498
- Publication date Sep 16, 2004
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dielectric stack
- Publication number 20040150069
- Publication date Aug 5, 2004
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Test structure
- Publication number 20040096995
- Publication date May 20, 2004
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buffer metal layer
- Publication number 20040072414
- Publication date Apr 15, 2004
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Test structure
- Publication number 20040043656
- Publication date Mar 4, 2004
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS

Qwai H. Low

Person

Patents Grantslast 30 patents

3D-interconnect

3D-interconnect

3D-interconnect

Low cost hybrid high density package

Low cost hybrid high density package

Low cost hybrid high density package

Method of manufacturing an electronic device package

Area array quad flat no-lead (QFN) package

Flip-chip QFN structure using etched lead frame

Electronic device package and method of manufacture

Package with power and ground through via

Lead frame design to improve reliability

Heat dissipation for integrated circuit

Wire bonding over active circuits

Electronic device package and method of manufacture

Eliminate IMC cracking in post wirebonded dies: macro level stress...

Heat spreader in integrated circuit package

Integrated heatspreader for use in wire bonded ball grid array semi...

Test structure for detecting bonding-induced cracks

Dielectric stack

Test structure

Buffer metal layer

Slotted bonding pad

Bonding pad for low k dielectric

Test structure for detecting bonding-induced cracks

Bonding pad isolation

Integrated circuit package

Integrated circuit having dedicated probe pads for use in testing d...

Molded tape ball grid array package

Tape design to reduce warpage

Patents Applicationslast 30 patents

3D-INTERCONNECT

3d-Interconnect

3D-Interconnect

3D-INTERCONNECT

Low cost hybrid high density package

LOW COST HYBRID HIGH DENSITY PACKAGE

LEAD FRAME DESIGN TO IMPROVE RELIABILITY

LOW COST HYBRID HIGH DENSITY PACKAGE

AREA ARRAY QFN

FLIP-CHIP QFN STRUCTURE USING ETCHED LEAD FRAME

FLIP-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME USING ABLATION

ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE

LEAD FRAME DESIGN TO IMPROVE RELIABILITY

ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE

Package with Power and Ground Through Via

Heat Dissipation For Integrated Circuit

WIRE BONDING OVER ACTIVE CIRCUITS

Eliminate IMC cracking in post wirebonded dies: macro level stress...

Bond pad structure for gold wire bonding to copper low K dielectric...

Integrated heatspreader for use in wire bonded ball grid array semi...

Heat spreader in integrated circuit package

Test structure for detecting bonding-induced cracks

Wire bonding to full array bonding pads on active circuitry

Dielectric stack

Test structure

Buffer metal layer

Test structure