Radu Pitigoi-Aron

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for chip operation using serial peripheral inte...
- Patent number 11,847,087
- Issue date Dec 19, 2023
- QUALCOMM Incorporated
- Lalan Jee Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error signaling windows for phase-differential protocols
- Patent number 11,531,608
- Issue date Dec 20, 2022
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
I2C bus architecture using shared clock and dedicated data lines
- Patent number 11,520,729
- Issue date Dec 6, 2022
- QUALCOMM Incorporated
- Lalan Jee Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Batch operation across an interface
- Patent number 11,513,991
- Issue date Nov 29, 2022
- QUALCOMM Incorporated
- Richard Dominic Wietfeldt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulse amplitude modulation (PAM) encoding for a communication bus
- Patent number 11,356,314
- Issue date Jun 7, 2022
- QUALCOMM Incorporated
- Lalan Jee Mishra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
I3C single data rate write flow control
- Patent number 11,023,408
- Issue date Jun 1, 2021
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency optimized I3C virtual GPIO with configurable operating mode...
- Patent number 10,733,121
- Issue date Aug 4, 2020
- QUALCOMM Incorporated
- Lalan Jee Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for synchronizing slave devices
- Patent number 10,707,984
- Issue date Jul 7, 2020
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-datagram critical-signaling using pulse-count-modulation for I3C...
- Patent number 10,693,674
- Issue date Jun 23, 2020
- QUALCOMM Incorporated
- Lalan Jee Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast termination of multilane single data rate transactions
- Patent number 10,684,981
- Issue date Jun 16, 2020
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilane heterogeneous serial bus
- Patent number 10,579,581
- Issue date Mar 3, 2020
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic optimal data sampling time on a multi-drop bus
- Patent number 10,572,438
- Issue date Feb 25, 2020
- QUALCOMM Incorporated
- Lalan Jee Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communicating heterogeneous virtual general-purpose input/output me...
- Patent number 10,515,044
- Issue date Dec 24, 2019
- QUALCOMM Incorporated
- Richard Dominic Wietfeldt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-protocol dynamic address allocation
- Patent number 10,482,057
- Issue date Nov 19, 2019
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sensors global bus
- Patent number 10,452,603
- Issue date Oct 22, 2019
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sensors global bus
- Patent number 10,417,172
- Issue date Sep 17, 2019
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data lane validation procedure for multilane protocols
- Patent number 10,402,365
- Issue date Sep 3, 2019
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically adjustable multi-line bus shared by multi-protocol devices
- Patent number 10,241,955
- Issue date Mar 26, 2019
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
General purpose input/output (GPIO) signal bridging with I3C bus in...
- Patent number 10,140,242
- Issue date Nov 27, 2018
- QUALCOMM Incorporated
- Lalan Jee Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test for 50 nanosecond spike filter
- Patent number 10,108,511
- Issue date Oct 23, 2018
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Time-sequenced multi-device address assignment
- Patent number 10,057,209
- Issue date Aug 21, 2018
- QUALCOMM Incorporated
- Lalan Jee Mishra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamically adjustable multi-line bus shared by multi-protocol devices
- Patent number 10,007,628
- Issue date Jun 26, 2018
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
N-base numbers to physical wire states symbols translation method
- Patent number 9,996,483
- Issue date Jun 12, 2018
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simultaneous edge toggling immunity circuit for multi-mode bus
- Patent number 9,990,330
- Issue date Jun 5, 2018
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Sensors global bus
- Patent number 9,921,998
- Issue date Mar 20, 2018
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for reducing energy consumption of a heart rate...
- Patent number 9,888,857
- Issue date Feb 13, 2018
- QUALCOMM Incorporated
- Ramin Samadani
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Variable frame length virtual GPIO with a modified UART interface
- Patent number 9,880,965
- Issue date Jan 30, 2018
- QUALCOMM Incorporated
- Lalan Jee Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sensors global bus
- Patent number 9,734,121
- Issue date Aug 15, 2017
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for supplying power at startup
- Patent number 9,502,957
- Issue date Nov 22, 2016
- Marvell World Trade Ltd.
- Ravishanker Krishnamoorthy
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Dimmer circuit for electronic loads
- Patent number 9,497,807
- Issue date Nov 15, 2016
- Marvell World Trade Ltd.
- Radu Pitigoi-Aron
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Patents Applicationslast 30 patents

Information Patent Application
ASYNCHRONOUS DOUBLE DATA-LANE DDR (ADL-DDR)
- Publication number 20250199992
- Publication date Jun 19, 2025
- QUALCOMM Incorporated
- Lalan Jee MISHRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASED RADIO FREQUENCY FRONT-END (RFFE) THROUGHPUT USING PORT AG...
- Publication number 20240089195
- Publication date Mar 14, 2024
- QUALCOMM Incorporated
- Lalan Jee MISHRA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEMS AND METHODS FOR CHIP OPERATION USING SERIAL PERIPHERAL INTE...
- Publication number 20230083877
- Publication date Mar 16, 2023
- QUALCOMM Incorporated
- Lalan Jee Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I2C BUS ARCHITECTURE USING SHARED CLOCK AND DEDICATED DATA LINES
- Publication number 20220358079
- Publication date Nov 10, 2022
- QUALCOMM Incorporated
- Lalan Jee MISHRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PULSE AMPLITUDE MODULATION (PAM) ENCODING FOR A COMMUNICATION BUS
- Publication number 20220123987
- Publication date Apr 21, 2022
- QUALCOMM Incorporated
- Lalan Jee Mishra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
BATCH OPERATION ACROSS AN INTERFACE
- Publication number 20220107912
- Publication date Apr 7, 2022
- QUALCOMM Incorporated
- Richard Dominic Wietfeldt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR SIGNALING WINDOWS FOR PHASE-DIFFERENTIAL PROTOCOLS
- Publication number 20220091952
- Publication date Mar 24, 2022
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIME-DIVISION MULTIPLEXING (TDM) DATA TRANSFER ON SERIAL INTERFACES
- Publication number 20200201808
- Publication date Jun 25, 2020
- QUALCOMM Incorporated
- Sharon GRAIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTILANE HETEROGENEOUS SERIAL BUS
- Publication number 20200142854
- Publication date May 7, 2020
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCED HIGH DATA RATE TECHNIQUE FOR I3C
- Publication number 20200097434
- Publication date Mar 26, 2020
- QUALCOMM Incorporated
- Lalan Jee Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I3C SINGLE DATA RATE WRITE FLOW CONTROL
- Publication number 20190377702
- Publication date Dec 12, 2019
- QUALCOMM Incorporated
- Radu PITIGOI-ARON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST TERMINATION OF MULTILANE SINGLE DATA RATE TRANSACTIONS
- Publication number 20190354505
- Publication date Nov 21, 2019
- QUALCOMM Incorporated
- Radu PITIGOI-ARON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST TERMINATION OF MULTILANE DOUBLE DATA RATE TRANSACTIONS
- Publication number 20190356412
- Publication date Nov 21, 2019
- QUALCOMM Incorporated
- Radu PITIGOI-ARON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LATENCY OPTIMIZED I3C VIRTUAL GPIO WITH CONFIGURABLE OPERATING MODE...
- Publication number 20190347225
- Publication date Nov 14, 2019
- QUALCOMM Incorporated
- Lalan Jee MISHRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTILANE HETEROGENUOUS SERIAL BUS
- Publication number 20190266122
- Publication date Aug 29, 2019
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-DATAGRAM CRITICAL-SIGNALING USING PULSE-COUNT-MODULATION FOR I3C...
- Publication number 20190238362
- Publication date Aug 1, 2019
- QUALCOMM Incorporated
- Lalan Jee Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA LANE VALIDATION PROCEDURE FOR MULTILANE PROTOCOLS
- Publication number 20190220436
- Publication date Jul 18, 2019
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIORITY SCHEME FOR FAST ARBITRATION PROCEDURES
- Publication number 20190213165
- Publication date Jul 11, 2019
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-DESTRUCTIVE OUTSIDE DEVICE ALERTS FOR MULTI-LANE I3C
- Publication number 20190171609
- Publication date Jun 6, 2019
- QUALCOMM Incorporated
- Lalan Jee MISHRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ADJUSTABLE MULTI-LINE BUS SHARED BY MULTI-PROTOCOL DEVICES
- Publication number 20190146944
- Publication date May 16, 2019
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENEOUS VIRTUAL GENERAL-PURPOSE INPUT/OUTPUT
- Publication number 20190129881
- Publication date May 2, 2019
- QUALCOMM Incorporated
- Richard Dominic Wietfeldt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARITY BITS LOCATION ON I3C MULTILANE BUS
- Publication number 20190095273
- Publication date Mar 28, 2019
- QUALCOMM Incorporated
- Sharon GRAIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATED I3C STOP INITIATED BY A THIRD PARTY
- Publication number 20190018818
- Publication date Jan 17, 2019
- QUALCOMM Incorporated
- Sharon GRAIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR SYNCHRONIZING SLAVE DEVICES
- Publication number 20190020433
- Publication date Jan 17, 2019
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SLAVE-TO-SLAVE COMMUNICATION IN I3C BUS TOPOLOGY
- Publication number 20180357199
- Publication date Dec 13, 2018
- QUALCOMM Incorporated
- Lalan Jee Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ASYNCHRONOUS EVENT TIMESTAMPING
- Publication number 20180224887
- Publication date Aug 9, 2018
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENSORS GLOBAL BUS
- Publication number 20180225253
- Publication date Aug 9, 2018
- QUALCOMM Incorporated
- Radu PITIGOI-ARON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA TRANSFER ENDING IN PHASE DIFFERENTIAL MODES
- Publication number 20180181532
- Publication date Jun 28, 2018
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENDING WRITE DATA TRANSFER IN I3C HDR-DDR MODE
- Publication number 20180181533
- Publication date Jun 28, 2018
- QUALCOMM Incorporated
- Radu Pitigoi-Aron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARD RESET OVER I3C BUS
- Publication number 20180173665
- Publication date Jun 21, 2018
- QUALCOMM Incorporated
- Lalan Jee Mishra
- G06 - COMPUTING CALCULATING COUNTING

Radu Pitigoi-Aron

Person

Patents Grantslast 30 patents

Systems and methods for chip operation using serial peripheral inte...

Error signaling windows for phase-differential protocols

I2C bus architecture using shared clock and dedicated data lines

Batch operation across an interface

Pulse amplitude modulation (PAM) encoding for a communication bus

I3C single data rate write flow control

Latency optimized I3C virtual GPIO with configurable operating mode...

Techniques for synchronizing slave devices

In-datagram critical-signaling using pulse-count-modulation for I3C...

Fast termination of multilane single data rate transactions

Multilane heterogeneous serial bus

Dynamic optimal data sampling time on a multi-drop bus

Communicating heterogeneous virtual general-purpose input/output me...

Multi-protocol dynamic address allocation

Sensors global bus

Sensors global bus

Data lane validation procedure for multilane protocols

Dynamically adjustable multi-line bus shared by multi-protocol devices

General purpose input/output (GPIO) signal bridging with I3C bus in...

Test for 50 nanosecond spike filter

Time-sequenced multi-device address assignment

Dynamically adjustable multi-line bus shared by multi-protocol devices

N-base numbers to physical wire states symbols translation method

Simultaneous edge toggling immunity circuit for multi-mode bus

Sensors global bus

Methods and systems for reducing energy consumption of a heart rate...

Variable frame length virtual GPIO with a modified UART interface

Sensors global bus

System and method for supplying power at startup

Dimmer circuit for electronic loads

Patents Applicationslast 30 patents

ASYNCHRONOUS DOUBLE DATA-LANE DDR (ADL-DDR)

INCREASED RADIO FREQUENCY FRONT-END (RFFE) THROUGHPUT USING PORT AG...

SYSTEMS AND METHODS FOR CHIP OPERATION USING SERIAL PERIPHERAL INTE...

I2C BUS ARCHITECTURE USING SHARED CLOCK AND DEDICATED DATA LINES

PULSE AMPLITUDE MODULATION (PAM) ENCODING FOR A COMMUNICATION BUS

BATCH OPERATION ACROSS AN INTERFACE

ERROR SIGNALING WINDOWS FOR PHASE-DIFFERENTIAL PROTOCOLS

TIME-DIVISION MULTIPLEXING (TDM) DATA TRANSFER ON SERIAL INTERFACES

MULTILANE HETEROGENEOUS SERIAL BUS

ENHANCED HIGH DATA RATE TECHNIQUE FOR I3C

I3C SINGLE DATA RATE WRITE FLOW CONTROL

FAST TERMINATION OF MULTILANE SINGLE DATA RATE TRANSACTIONS

FAST TERMINATION OF MULTILANE DOUBLE DATA RATE TRANSACTIONS

LATENCY OPTIMIZED I3C VIRTUAL GPIO WITH CONFIGURABLE OPERATING MODE...

MULTILANE HETEROGENUOUS SERIAL BUS

IN-DATAGRAM CRITICAL-SIGNALING USING PULSE-COUNT-MODULATION FOR I3C...

DATA LANE VALIDATION PROCEDURE FOR MULTILANE PROTOCOLS

PRIORITY SCHEME FOR FAST ARBITRATION PROCEDURES

NON-DESTRUCTIVE OUTSIDE DEVICE ALERTS FOR MULTI-LANE I3C

DYNAMICALLY ADJUSTABLE MULTI-LINE BUS SHARED BY MULTI-PROTOCOL DEVICES

HETEROGENEOUS VIRTUAL GENERAL-PURPOSE INPUT/OUTPUT

PARITY BITS LOCATION ON I3C MULTILANE BUS

ACCELERATED I3C STOP INITIATED BY A THIRD PARTY

TECHNIQUES FOR SYNCHRONIZING SLAVE DEVICES

SLAVE-TO-SLAVE COMMUNICATION IN I3C BUS TOPOLOGY

APPARATUS AND METHOD FOR ASYNCHRONOUS EVENT TIMESTAMPING

SENSORS GLOBAL BUS

DATA TRANSFER ENDING IN PHASE DIFFERENTIAL MODES

ENDING WRITE DATA TRANSFER IN I3C HDR-DDR MODE

HARD RESET OVER I3C BUS