Rafael Czernek Camarota

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
PLD package with coordinated RFID tag
- Patent number 8,502,676
- Issue date Aug 6, 2013
- Altera Corporation
- Rafael Czernek Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-touch decoder for digital resistive screen overlay
- Patent number 8,330,741
- Issue date Dec 11, 2012
- Altera Corporation
- Rafael Czernek Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with differential communications support
- Patent number 8,086,922
- Issue date Dec 27, 2011
- Altera Corporation
- Rafael Czernek Camarota
- G11 - INFORMATION STORAGE
Information Patent Grant
PLD package with coordinated RFID TAG
- Patent number 8,081,079
- Issue date Dec 20, 2011
- Altera Corporation
- Rafael Czernek Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with differential communications support
- Patent number 7,958,416
- Issue date Jun 7, 2011
- Altera Corporation
- Rafael Czernek Camarota
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage tolerance emulation using voltage clamp for oxide stre...
- Patent number 7,733,159
- Issue date Jun 8, 2010
- Altera Corporation
- Rafael Camarota
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for using boundary scan in a programmable logic d...
- Patent number 7,550,995
- Issue date Jun 23, 2009
- Altera Corporation
- Patrick Guilloteau
- G01 - MEASURING TESTING
Information Patent Grant
Programmable logic device with on-chip nonvolatile user memory
- Patent number 7,550,994
- Issue date Jun 23, 2009
- Altera Corporation
- Rafael C. Camarota
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device with differential communications support
- Patent number 7,505,331
- Issue date Mar 17, 2009
- Altera Corporation
- Rafael Czernek Camarota
- G11 - INFORMATION STORAGE
Information Patent Grant
CPLD for multi-wire keyboard decode with timed power control circuit
- Patent number 7,486,106
- Issue date Feb 3, 2009
- Altera Corporation
- Rafael Czernek Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input buffer with selectable threshold and hysteresis option
- Patent number 7,276,935
- Issue date Oct 2, 2007
- Altera Corporation
- Rafael C. Camarota
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for using boundary scan in a programmable logic d...
- Patent number 7,248,070
- Issue date Jul 24, 2007
- Altera Corporation
- Patrick Guilloteau
- G01 - MEASURING TESTING
Information Patent Grant
Techniques for combining volatile and non-volatile programmable log...
- Patent number 7,242,218
- Issue date Jul 10, 2007
- Altera Corporation
- Rafael Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with on-chip nonvolatile user memory
- Patent number 7,190,190
- Issue date Mar 13, 2007
- Altera Corporation
- Rafael C. Camarota
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic with programmable volatility
- Patent number 7,154,297
- Issue date Dec 26, 2006
- Altera Corporation
- Rafael C. Camarota
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Input buffer with selectable threshold and hysteresis option
- Patent number 7,023,238
- Issue date Apr 4, 2006
- Altera Corporation
- Rafael C. Camarota
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic core adapter
- Patent number 6,744,274
- Issue date Jun 1, 2004
- Stretch, Inc.
- Jeffrey M. Arnold
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device
- Patent number 6,462,576
- Issue date Oct 8, 2002
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient and robust random access memory cell suitable for program...
- Patent number 6,418,045
- Issue date Jul 9, 2002
- Adaptive Silicon, Inc.
- Rafael C. Camarota
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device
- Patent number 6,294,925
- Issue date Sep 25, 2001
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient and robust random access memory cell suitable for program...
- Patent number 6,292,388
- Issue date Sep 18, 2001
- Adaptive Silicon, Inc.
- Rafael C. Camarota
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for minimizing instantaneous currents when driving bus signals
- Patent number 6,278,311
- Issue date Aug 21, 2001
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device
- Patent number 6,255,847
- Issue date Jul 3, 2001
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable integrated circuit device with slew control and skew c...
- Patent number 6,229,336
- Issue date May 8, 2001
- Lattice Semiconductor Corporation
- Bradley Felton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable output voltage levels
- Patent number 6,066,977
- Issue date May 23, 2000
- Lattice Semiconductor Corporation
- Bradley Felton
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
PLD PACKAGE WITH COORDINATED RFID TAG
- Publication number 20120075081
- Publication date Mar 29, 2012
- Rafael Czernek Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for combining volatile and non-volatile programmable log...
- Publication number 20060119384
- Publication date Jun 8, 2006
- Altera Corporation
- Rafael Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for self testing programmable logic arrays
- Publication number 20050039098
- Publication date Feb 17, 2005
- Rafael C. Camarota
- G01 - MEASURING TESTING
Information Patent Application
Built-in self test for a programmable logic device using linear fee...
- Publication number 20020078412
- Publication date Jun 20, 2002
- Yongjiang Wang
- G01 - MEASURING TESTING
Information Patent Application
Efficient and robust random access memory cell suitable for program...
- Publication number 20020001222
- Publication date Jan 3, 2002
- Rafael C. Camarota
- G11 - INFORMATION STORAGE

Rafael Czernek Camarota

Person

Patents Grantslast 30 patents

PLD package with coordinated RFID tag

Multi-touch decoder for digital resistive screen overlay

Programmable logic device with differential communications support

PLD package with coordinated RFID TAG

Programmable logic device with differential communications support

High voltage tolerance emulation using voltage clamp for oxide stre...

Method and system for using boundary scan in a programmable logic d...

Programmable logic device with on-chip nonvolatile user memory

Programmable logic device with differential communications support

CPLD for multi-wire keyboard decode with timed power control circuit

Input buffer with selectable threshold and hysteresis option

Method and system for using boundary scan in a programmable logic d...

Techniques for combining volatile and non-volatile programmable log...

Programmable logic device with on-chip nonvolatile user memory

Programmable logic with programmable volatility

Input buffer with selectable threshold and hysteresis option

Programmable logic core adapter

Programmable logic device

Efficient and robust random access memory cell suitable for program...

Programmable logic device

Efficient and robust random access memory cell suitable for program...

Method for minimizing instantaneous currents when driving bus signals

Programmable logic device

Programmable integrated circuit device with slew control and skew c...

Programmable output voltage levels

Patents Applicationslast 30 patents

PLD PACKAGE WITH COORDINATED RFID TAG

Techniques for combining volatile and non-volatile programmable log...

Apparatus and method for self testing programmable logic arrays

Built-in self test for a programmable logic device using linear fee...

Efficient and robust random access memory cell suitable for program...