Rahul Agarwal

Person

Waterford, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of manufacturing a 3 color LED integrated Si CMOS driver waf...
- Patent number 10,193,011
- Issue date Jan 29, 2019
- GLOBALFOUNDRIES Inc.
- Srinivasa Banna
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside spacer structures for improved thermal performance
- Patent number 10,153,224
- Issue date Dec 11, 2018
- GLOBALFOUNDRIES Inc.
- Rahul Agarwal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer bond interconnect structures
- Patent number 10,026,883
- Issue date Jul 17, 2018
- GLOBALFOUNDRIES Inc.
- Luke England
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interposer and methods of forming and testing an interposer
- Patent number 9,601,424
- Issue date Mar 21, 2017
- GLOBALFOUNDRIES, INC.
- Rahul Agarwal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer backside redistribution layer warpage control
- Patent number 9,553,058
- Issue date Jan 24, 2017
- GLOBALFOUNDRIES Inc.
- Luke England
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer support system for 3D packaging
- Patent number 9,013,039
- Issue date Apr 21, 2015
- GLOBALFOUNDRIES Inc.
- Rahul Agarwal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of thinning and/or dicing semiconducting substrates having...
- Patent number 8,669,166
- Issue date Mar 11, 2014
- GLOBALFOUNDRIES Inc.
- Rahul Agarwal
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF MANUFACTURING A 3 COLOR LED INTEGRATED SI CMOS DRIVER WAF...
- Publication number 20190019915
- Publication date Jan 17, 2019
- GLOBALFOUNDRIES INC.
- Srinivasa BANNA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER BOND INTERCONNECT STRUCTURES
- Publication number 20180175266
- Publication date Jun 21, 2018
- GLOBALFOUNDRIES INC.
- Luke ENGLAND
- F21 - LIGHTING
Information Patent Application
BACKSIDE SPACER STRUCTURES FOR IMPROVED THERMAL PERFORMANCE
- Publication number 20180076110
- Publication date Mar 15, 2018
- GLOBALFOUNDRIES INC.
- Rahul AGARWAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERPOSER AND METHODS OF FORMING AND TESTING AN INTERPOSER
- Publication number 20160300788
- Publication date Oct 13, 2016
- GLOBALFOUNDRIES, Inc.
- Rahul Agarwal
- G01 - MEASURING TESTING
Information Patent Application
CRACKSTOPS FOR BULK SEMICONDUCTOR WAFERS
- Publication number 20150371956
- Publication date Dec 24, 2015
- GLOBALFOUNDRIES INC.
- Rahul Agarwal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER SUPPORT SYSTEM FOR 3D PACKAGING
- Publication number 20150035140
- Publication date Feb 5, 2015
- GLOBAL FOUNDRIES Inc.
- Rahul AGARWAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SEMICONDUCTOR DEVICES WITH A GLASS WINDOW WAFER HAVING AN E...
- Publication number 20140070405
- Publication date Mar 13, 2014
- GLOBALFOUNDRIES INC.
- Rahul Agarwal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF THINNING AND/OR DICING SEMICONDUCTING SUBSTRATES HAVING...
- Publication number 20140051233
- Publication date Feb 20, 2014
- GLOBALFOUNDRIES INC.
- Rahul Agarwal
- H01 - BASIC ELECTRIC ELEMENTS

Rahul Agarwal

Person

Patents Grantslast 30 patents

Method of manufacturing a 3 color LED integrated Si CMOS driver waf...

Backside spacer structures for improved thermal performance

Wafer bond interconnect structures

Interposer and methods of forming and testing an interposer

Wafer backside redistribution layer warpage control

Wafer support system for 3D packaging

Methods of thinning and/or dicing semiconducting substrates having...

Patents Applicationslast 30 patents

METHOD OF MANUFACTURING A 3 COLOR LED INTEGRATED SI CMOS DRIVER WAF...

WAFER BOND INTERCONNECT STRUCTURES

BACKSIDE SPACER STRUCTURES FOR IMPROVED THERMAL PERFORMANCE

INTERPOSER AND METHODS OF FORMING AND TESTING AN INTERPOSER

CRACKSTOPS FOR BULK SEMICONDUCTOR WAFERS

WAFER SUPPORT SYSTEM FOR 3D PACKAGING

STACKED SEMICONDUCTOR DEVICES WITH A GLASS WINDOW WAFER HAVING AN E...

METHODS OF THINNING AND/OR DICING SEMICONDUCTING SUBSTRATES HAVING...