Rahul Sahu

Person

Uttar Pradesh, IN

People

Patents Grantslast 30 patents

Information Patent Grant
High-speed multi-port memory supporting collision
- Patent number 12,183,393
- Issue date Dec 31, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Power supply circuit with reduced leakage current
- Patent number 12,047,073
- Issue date Jul 23, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory circuit architecture with multiplexing between memory banks
- Patent number 12,020,766
- Issue date Jun 25, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory write assist with reduced switching power
- Patent number 12,020,746
- Issue date Jun 25, 2024
- QUALCOMM Incorporated
- Rejeesh Ammanath Vijayan
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power and robust level-shifting pulse latch for dual-power memo...
- Patent number 11,972,834
- Issue date Apr 30, 2024
- QUALCOMM Incorporated
- Adithya Bhaskaran
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed multi-port memory supporting collision
- Patent number 11,955,169
- Issue date Apr 9, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with scan chain testing of column redundancy logic and multi...
- Patent number 11,935,606
- Issue date Mar 19, 2024
- QUALCOMM Incorporated
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with efficient DVS controlled by asynchronous inputs
- Patent number 11,837,313
- Issue date Dec 5, 2023
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for control signal latching in memories
- Patent number 11,152,921
- Issue date Oct 19, 2021
- QUALCOMM Incorporated
- Veerabhadra Rao Boda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Write assist circuitry for memory
- Patent number 11,049,552
- Issue date Jun 29, 2021
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Area efficient write data path circuit for SRAM yield enhancement
- Patent number 10,867,668
- Issue date Dec 15, 2020
- QUALCOMM Incorporated
- Sharad Kumar Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory core power-up with reduced peak current
- Patent number 10,839,866
- Issue date Nov 17, 2020
- QUALCOMM Incorporated
- Shiba Narayan Mohanty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SRAM write yield enhancement with pull-up strength modulation
- Patent number 10,811,086
- Issue date Oct 20, 2020
- QUALCOMM Incorporated
- Shiba Narayan Mohanty
- G11 - INFORMATION STORAGE
Information Patent Grant
Access assist with wordline adjustment with tracking cell
- Patent number 10,811,088
- Issue date Oct 20, 2020
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Boost generation circuitry for memory
- Patent number 10,614,865
- Issue date Apr 7, 2020
- QUALCOMM Incorporated
- Shiba Narayan Mohanty
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline adjustment scheme
- Patent number 9,928,898
- Issue date Mar 27, 2018
- QUALCOMM Incorporated
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Grant
Write driver circuitry to reduce leakage of negative boost charge
- Patent number 9,916,892
- Issue date Mar 13, 2018
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Write data path to reduce charge leakage of negative boost
- Patent number 9,865,337
- Issue date Jan 9, 2018
- QUALCOMM Incorporated
- Fahad Ahmed
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture to improve write-ability in SRAM
- Patent number 9,721,650
- Issue date Aug 1, 2017
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive negative bit line write assist
- Patent number 9,455,028
- Issue date Sep 27, 2016
- QUALCOMM Incorporated
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory sense amplifier and column pre-charger
- Patent number 9,281,055
- Issue date Mar 8, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit line write assist for static random access memory architectures
- Patent number 9,177,633
- Issue date Nov 3, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Rajiv Kumar Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual rail single-ended read data paths for static random access mem...
- Patent number 9,177,635
- Issue date Nov 3, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Differential latch word line assist for SRAM
- Patent number 9,111,637
- Issue date Aug 18, 2015
- Avago Technologies General IP Singapore) Pte Ltd
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having control circuitry for write tracking using fee...
- Patent number 9,047,936
- Issue date Jun 2, 2015
- LSI Corporation
- Kamal Chandwani
- G11 - INFORMATION STORAGE
Information Patent Grant
Address decoding circuits for reducing address and memory enable se...
- Patent number 8,923,090
- Issue date Dec 30, 2014
- LSI Corporation
- Donald A. Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory having self-timed edge-detection write tracking
- Patent number 8,923,069
- Issue date Dec 30, 2014
- LSI Corporation
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-charge tracking of global read lines in high speed SRAM
- Patent number 8,879,303
- Issue date Nov 4, 2014
- LSI Corporation
- Kamal Chandwani
- G11 - INFORMATION STORAGE
Information Patent Grant
Margin free PVT tolerant fast self-timed sense amplifier reset circuit
- Patent number 8,830,766
- Issue date Sep 9, 2014
- LSI Corporation
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Grant
Write-tracking circuitry for memory devices
- Patent number 8,811,070
- Issue date Aug 19, 2014
- LSI Corporation
- Dharmendra Kumar Rai
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier O...
- Publication number 20240321376
- Publication date Sep 26, 2024
- QUALCOMM Incorporated
- Debarghya DUTTA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS
- Publication number 20240312496
- Publication date Sep 19, 2024
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with Scan Chain Testing of Column Redundancy Logic and Multi...
- Publication number 20240221853
- Publication date Jul 4, 2024
- QUALCOMM Incorporated
- Rahul SAHU
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION
- Publication number 20240221828
- Publication date Jul 4, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS
- Publication number 20230290387
- Publication date Sep 14, 2023
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Write Assist with Reduced Switching Power
- Publication number 20230267993
- Publication date Aug 24, 2023
- QUALCOMM Incorporated
- Rejeesh Ammanath Vijayan
- G11 - INFORMATION STORAGE
Information Patent Application
POWER SUPPLY CIRCUIT WITH REDUCED LEAKAGE CURRENT
- Publication number 20230179183
- Publication date Jun 8, 2023
- QUALCOMM Incorporated
- Pradeep RAJ
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY WITH EFFICIENT DVS CONTROLLED BY ASYNCHRONOUS INPUTS
- Publication number 20230139283
- Publication date May 4, 2023
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH SCAN CHAIN TESTING OF COLUMN REDUNDANCY LOGIC AND MULTI...
- Publication number 20230005556
- Publication date Jan 5, 2023
- QUALCOMM Incorporated
- Rahul SAHU
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION
- Publication number 20220310156
- Publication date Sep 29, 2022
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
Low Power and Robust Level-Shifting Pulse Latch for Dual-Power Memo...
- Publication number 20220293148
- Publication date Sep 15, 2022
- QUALCOMM Incorporated
- Adithya Bhaskaran
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CORE POWER-UP WITH REDUCED PEAK CURRENT
- Publication number 20200381023
- Publication date Dec 3, 2020
- QUALCOMM Incorporated
- Shiba Narayan MOHANTY
- G11 - INFORMATION STORAGE
Information Patent Application
ACCESS ASSIST WITH WORDLINE ADJUSTMENT WITH TRACKING CELL
- Publication number 20200294580
- Publication date Sep 17, 2020
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Application
BOOST GENERATION CIRCUITRY FOR MEMORY
- Publication number 20200126604
- Publication date Apr 23, 2020
- QUALCOMM Incorporated
- Shiba Narayan MOHANTY
- G11 - INFORMATION STORAGE
Information Patent Application
AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT
- Publication number 20190108872
- Publication date Apr 11, 2019
- QUALCOMM Incorporated
- Sharad Kumar GUPTA
- G11 - INFORMATION STORAGE
Information Patent Application
WORDLINE ADJUSTMENT SCHEME
- Publication number 20170287551
- Publication date Oct 5, 2017
- QUALCOMM Incorporated
- Rahul SAHU
- G11 - INFORMATION STORAGE
Information Patent Application
WORD LINE DECODERS FOR DUAL RAIL STATIC RANDOM ACCESS MEMORIES
- Publication number 20150302918
- Publication date Oct 22, 2015
- LSI Corporation
- Rajiv Kumar Roy
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Sense Amplifier And Column Pre-Charger
- Publication number 20150269990
- Publication date Sep 24, 2015
- LSI Corporation
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Application
BIT LINE WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARCHITECTURES
- Publication number 20150255148
- Publication date Sep 10, 2015
- LSI Corporation
- Rajiv Kumar Roy
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED READ/WRITE TRACKING IN SRAM
- Publication number 20150213881
- Publication date Jul 30, 2015
- LSI Corporation
- Dharmendra Kumar Rai
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES
- Publication number 20150138864
- Publication date May 21, 2015
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
INTERLEAVED WRITE ASSIST FOR HIERARCHICAL BITLINE SRAM ARCHITECTURES
- Publication number 20150138863
- Publication date May 21, 2015
- LSI Corporation
- Rajiv Kumar Roy
- G11 - INFORMATION STORAGE
Information Patent Application
Bit-Line Discharge Assistance in Memory Devices
- Publication number 20150085592
- Publication date Mar 26, 2015
- LSI Corporation
- Dharmendra Kumar Rai
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE-TRACKING CIRCUITRY FOR MEMORY DEVICES
- Publication number 20140233302
- Publication date Aug 21, 2014
- LSI Corporation
- Dharmendra Kumar Rai
- G11 - INFORMATION STORAGE
Information Patent Application
MARGIN FREE PVT TOLERANT FAST SELF-TIMED SENSE AMPLIFIER RESET CIRCUIT
- Publication number 20140204683
- Publication date Jul 24, 2014
- LSI Corporation
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY HAVING SENSE AMPLIFIER FOR OUTPUT TRACKING BY CONTROLLED FEE...
- Publication number 20140204660
- Publication date Jul 24, 2014
- LSI Corporation
- Kamal Chandwani
- G11 - INFORMATION STORAGE
Information Patent Application
PRE-CHARGE TRACKING OF GLOBAL READ LINES IN HIGH SPEED SRAM
- Publication number 20140185366
- Publication date Jul 3, 2014
- LSI Corporation
- Kamal Chandwani
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH CLOCK GENERATION BASED ON SEGMENTED ADDRESS CHAN...
- Publication number 20140071783
- Publication date Mar 13, 2014
- LSI Corporation
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device Having Control Circuitry for Write Tracking Using Fee...
- Publication number 20130322190
- Publication date Dec 5, 2013
- LSI Corporation
- Kamal Chandwani
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY HAVING SELF-TIMED EDGE-DETECTION WRITE TRACKING
- Publication number 20130322193
- Publication date Dec 5, 2013
- LSI CORPORATION
- Rahul Sahu
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

High-speed multi-port memory supporting collision

Power supply circuit with reduced leakage current

Memory circuit architecture with multiplexing between memory banks

Memory write assist with reduced switching power

Low power and robust level-shifting pulse latch for dual-power memo...

High-speed multi-port memory supporting collision

Memory with scan chain testing of column redundancy logic and multi...

Memory with efficient DVS controlled by asynchronous inputs

Systems and methods for control signal latching in memories

Write assist circuitry for memory

Area efficient write data path circuit for SRAM yield enhancement

Memory core power-up with reduced peak current

SRAM write yield enhancement with pull-up strength modulation

Access assist with wordline adjustment with tracking cell

Boost generation circuitry for memory

Wordline adjustment scheme

Write driver circuitry to reduce leakage of negative boost charge

Write data path to reduce charge leakage of negative boost

Architecture to improve write-ability in SRAM

Adaptive negative bit line write assist

Memory sense amplifier and column pre-charger

Bit line write assist for static random access memory architectures

Dual rail single-ended read data paths for static random access mem...

Differential latch word line assist for SRAM

Memory device having control circuitry for write tracking using fee...

Address decoding circuits for reducing address and memory enable se...

Memory having self-timed edge-detection write tracking

Pre-charge tracking of global read lines in high speed SRAM

Margin free PVT tolerant fast self-timed sense amplifier reset circuit

Write-tracking circuitry for memory devices

Patents Applicationslast 30 patents

Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier O...

MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS

Memory with Scan Chain Testing of Column Redundancy Logic and Multi...

HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION

MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS

Memory Write Assist with Reduced Switching Power

POWER SUPPLY CIRCUIT WITH REDUCED LEAKAGE CURRENT

MEMORY WITH EFFICIENT DVS CONTROLLED BY ASYNCHRONOUS INPUTS

MEMORY WITH SCAN CHAIN TESTING OF COLUMN REDUNDANCY LOGIC AND MULTI...

HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION

Low Power and Robust Level-Shifting Pulse Latch for Dual-Power Memo...

MEMORY CORE POWER-UP WITH REDUCED PEAK CURRENT

ACCESS ASSIST WITH WORDLINE ADJUSTMENT WITH TRACKING CELL

BOOST GENERATION CIRCUITRY FOR MEMORY

AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT

WORDLINE ADJUSTMENT SCHEME

WORD LINE DECODERS FOR DUAL RAIL STATIC RANDOM ACCESS MEMORIES

Memory Sense Amplifier And Column Pre-Charger

BIT LINE WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARCHITECTURES

INTEGRATED READ/WRITE TRACKING IN SRAM

MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES

INTERLEAVED WRITE ASSIST FOR HIERARCHICAL BITLINE SRAM ARCHITECTURES

Bit-Line Discharge Assistance in Memory Devices

WRITE-TRACKING CIRCUITRY FOR MEMORY DEVICES

MARGIN FREE PVT TOLERANT FAST SELF-TIMED SENSE AMPLIFIER RESET CIRCUIT

MEMORY HAVING SENSE AMPLIFIER FOR OUTPUT TRACKING BY CONTROLLED FEE...

PRE-CHARGE TRACKING OF GLOBAL READ LINES IN HIGH SPEED SRAM

MEMORY DEVICE WITH CLOCK GENERATION BASED ON SEGMENTED ADDRESS CHAN...

Memory Device Having Control Circuitry for Write Tracking Using Fee...

MEMORY HAVING SELF-TIMED EDGE-DETECTION WRITE TRACKING