Rajarshi Mukherjee

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reset domain crossing detection and simulation
- Patent number 11,907,631
- Issue date Feb 20, 2024
- Synopsys, Inc.
- Fahim Rahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine learning (ML)-based static verification for derived hardwar...
- Patent number 11,467,851
- Issue date Oct 11, 2022
- Synopsys, Inc.
- Kaushik De
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Convergence centric coverage for clock domain crossing (CDC) jitter...
- Patent number 11,403,450
- Issue date Aug 2, 2022
- Synopsys, Inc.
- Anshu Malani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated root-cause analysis, visualization, and debugging of stat...
- Patent number 11,288,427
- Issue date Mar 29, 2022
- Synopsys, Inc.
- Sauresh Bhowmick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State table complexity reduction in a hierarchical verification flow
- Patent number 11,222,154
- Issue date Jan 11, 2022
- Synopsys, Inc.
- Kaushik De
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated root-cause analysis, visualization, and debugging of stat...
- Patent number 10,586,001
- Issue date Mar 10, 2020
- Synopsys, Inc.
- Sauresh Bhowmick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for generating reduced standard delay format file...
- Patent number 10,460,059
- Issue date Oct 29, 2019
- Cadence Design Systems, Inc.
- Akash Khandelwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accurate glitch detection
- Patent number 9,792,394
- Issue date Oct 17, 2017
- Synopsys, Inc.
- Kaushik De
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying inconsistent constraints
- Patent number 9,069,699
- Issue date Jun 30, 2015
- Synopsys, Inc.
- Dhiraj Goswami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for design verification and debugging of a comple...
- Patent number 7,383,168
- Issue date Jun 3, 2008
- Fujitsu Limited
- Rajarshi Mukherjee
- G01 - MEASURING TESTING
Information Patent Grant
System, method and computer program product for equivalence checkin...
- Patent number 7,350,168
- Issue date Mar 25, 2008
- Calypto Design Systems, Inc.
- Anmol Mathur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling events in a boolean satisfiability (SAT) solver
- Patent number 7,194,710
- Issue date Mar 20, 2007
- Fujitsu Limited
- Mukul R. Prasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing latch mapping of sequential circuits
- Patent number 7,032,192
- Issue date Apr 18, 2006
- Fujitsu Limited
- Mukul R. Prasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple error and fault diagnosis based on Xlists
- Patent number 6,532,440
- Issue date Mar 11, 2003
- Fujitsu Limited
- Vamsi Boppana
- G01 - MEASURING TESTING
Information Patent Grant
Verification of sequential circuits with same state encoding
- Patent number 6,408,424
- Issue date Jun 18, 2002
- Fujitsu Limited
- Rajarshi Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for verification of combinational circuits using a filtering...
- Patent number 6,301,687
- Issue date Oct 9, 2001
- Fujitsu Limited
- Jawahar Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for verification of combinational circuits using a filtering...
- Patent number 6,086,626
- Issue date Jul 11, 2000
- Fijutsu Limited
- Jawahar Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Topology-based computer-aided design system for digital circuits an...
- Patent number 5,649,165
- Issue date Jul 15, 1997
- Fujitsu Limited
- Jawahar Jain
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
GENERATING A REDUCED BLOCK MODEL VIEW ON-THE-FLY
- Publication number 20220327266
- Publication date Oct 13, 2022
- Synopsys, Inc.
- Mahantesh D. Narwade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESET DOMAIN CROSSING DETECTION AND SIMULATION
- Publication number 20220092244
- Publication date Mar 24, 2022
- Synopsys, Inc.
- Fahim RAHIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERGENCE CENTRIC COVERAGE FOR CLOCK DOMAIN CROSSING (CDC) JITTER...
- Publication number 20210209279
- Publication date Jul 8, 2021
- Synopsys, Inc.
- Anshu MALANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATE TABLE COMPLEXITY REDUCTION IN A HIERARCHICAL VERIFICATION FLOW
- Publication number 20210110093
- Publication date Apr 15, 2021
- Synopsys, Inc.
- Kaushik DE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automated Root-Cause Analysis, Visualization, and Debugging of Stat...
- Publication number 20200349311
- Publication date Nov 5, 2020
- Synopsys, Inc.
- Sauresh BHOWMICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automated Root-Cause Analysis, Visualization, and Debugging of Stat...
- Publication number 20190213288
- Publication date Jul 11, 2019
- Synopsys, Inc.
- Sauresh BHOWMICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCURATE GLITCH DETECTION
- Publication number 20170053051
- Publication date Feb 23, 2017
- Synopsys, Inc.
- Kaushik De
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IDENTIFYING INCONSISTENT CONSTRAINTS
- Publication number 20120253754
- Publication date Oct 4, 2012
- Synopsys, Inc.
- Dhiraj Goswami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduling events in a boolean satisfiability (SAT) solver
- Publication number 20050216871
- Publication date Sep 29, 2005
- Mukul R. Prasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing latch mapping of sequential circuits
- Publication number 20040237057
- Publication date Nov 25, 2004
- FUJITSU LIMITED
- Mukul R. Prasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for design verification
- Publication number 20040133409
- Publication date Jul 8, 2004
- Rajarshi Mukherjee
- G01 - MEASURING TESTING

Rajarshi Mukherjee

Person

Patents Grantslast 30 patents

Reset domain crossing detection and simulation

Machine learning (ML)-based static verification for derived hardwar...

Convergence centric coverage for clock domain crossing (CDC) jitter...

Automated root-cause analysis, visualization, and debugging of stat...

State table complexity reduction in a hierarchical verification flow

Automated root-cause analysis, visualization, and debugging of stat...

System and method for generating reduced standard delay format file...

Accurate glitch detection

Identifying inconsistent constraints

Method and system for design verification and debugging of a comple...

System, method and computer program product for equivalence checkin...

Scheduling events in a boolean satisfiability (SAT) solver

Performing latch mapping of sequential circuits

Multiple error and fault diagnosis based on Xlists

Verification of sequential circuits with same state encoding

Method for verification of combinational circuits using a filtering...

Method for verification of combinational circuits using a filtering...

Topology-based computer-aided design system for digital circuits an...

Patents Applicationslast 30 patents

GENERATING A REDUCED BLOCK MODEL VIEW ON-THE-FLY

RESET DOMAIN CROSSING DETECTION AND SIMULATION

CONVERGENCE CENTRIC COVERAGE FOR CLOCK DOMAIN CROSSING (CDC) JITTER...

STATE TABLE COMPLEXITY REDUCTION IN A HIERARCHICAL VERIFICATION FLOW

Automated Root-Cause Analysis, Visualization, and Debugging of Stat...

Automated Root-Cause Analysis, Visualization, and Debugging of Stat...

ACCURATE GLITCH DETECTION

METHOD AND APPARATUS FOR IDENTIFYING INCONSISTENT CONSTRAINTS

Scheduling events in a boolean satisfiability (SAT) solver

Performing latch mapping of sequential circuits

Method and system for design verification