Rajendra D. Pendse

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrating control circuits with light emissive circuits with diss...
- Patent number 12,224,271
- Issue date Feb 11, 2025
- Meta Platforms Technologies, LLC
- Rajendra D. Pendse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing thermal resistance and planarity of a display package
- Patent number 11,942,589
- Issue date Mar 26, 2024
- Meta Platforms Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Artificial reality system having system-on-a-chip (soc) integrated...
- Patent number 11,852,835
- Issue date Dec 26, 2023
- Meta Platforms Technologies, LLC
- Rajendra D. Pendse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating control circuits with light emissive circuits with diss...
- Patent number 11,842,989
- Issue date Dec 12, 2023
- Meta Platforms Technologies, LLC
- Rajendra D. Pendse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aligning a collimator assembly with LED arrays
- Patent number 11,668,942
- Issue date Jun 6, 2023
- Meta Platforms Technologies, LLC
- Rajendra D. Pendse
- G02 - OPTICS
Information Patent Grant
Artificial reality system having system-on-a-chip (SoC) integrated...
- Patent number 11,550,158
- Issue date Jan 10, 2023
- Meta Platforms Technologies, LLC
- Rajendra D. Pendse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated display devices
- Patent number 11,545,475
- Issue date Jan 3, 2023
- Meta Platforms Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Left and right projectors for display device
- Patent number 11,508,700
- Issue date Nov 22, 2022
- Meta Platforms Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Managing thermal resistance and planarity of a display package
- Patent number 11,362,251
- Issue date Jun 14, 2022
- Facebook Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Aligning a collimator assembly with LED arrays
- Patent number 11,287,656
- Issue date Mar 29, 2022
- Facebook Technologies, LLC
- Rajendra D. Pendse
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Thin 3D fan-out embedded wafer level package (EWLB) for application...
- Patent number 11,251,154
- Issue date Feb 15, 2022
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated display devices
- Patent number 11,037,915
- Issue date Jun 15, 2021
- Facebook Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacking of three-dimensional circuits including through-silicon-vias
- Patent number 10,700,041
- Issue date Jun 30, 2020
- Facebook Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin 3D fan-out embedded wafer level package (EWLB) for application...
- Patent number 10,692,836
- Issue date Jun 23, 2020
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming high routing density int...
- Patent number 10,580,749
- Issue date Mar 3, 2020
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming electrical interconnect...
- Patent number RE47600
- Issue date Sep 10, 2019
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
Information Patent Grant
Semiconductor device and method of forming flipchip interconnect st...
- Patent number 10,388,626
- Issue date Aug 20, 2019
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor device and method of forming electromagnetic (EM) shi...
- Patent number 10,388,612
- Issue date Aug 20, 2019
- STATS ChipPAC Pte. Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package on package (PoP) device comprising thermal interface materi...
- Patent number 10,002,857
- Issue date Jun 19, 2018
- QUALCOMM Incorporated
- Michael James Solimando
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bump-on-lead flip chip interconnection
- Patent number 9,922,915
- Issue date Mar 20, 2018
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of self-confinement of conductive b...
- Patent number 9,899,286
- Issue date Feb 20, 2018
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin 3D fan-out embedded wafer level package (EWLB) for application...
- Patent number 9,881,894
- Issue date Jan 30, 2018
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of self-confinement of conductive b...
- Patent number 9,865,556
- Issue date Jan 9, 2018
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming vertical interconnect st...
- Patent number 9,847,309
- Issue date Dec 19, 2017
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming pad layout for flipchip...
- Patent number 9,780,057
- Issue date Oct 3, 2017
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder joint flip chip interconnection having relief structure
- Patent number 9,773,685
- Issue date Sep 26, 2017
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming electromagnetic (EM) shi...
- Patent number 9,754,897
- Issue date Sep 5, 2017
- STATS ChipPAC, Pte. Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of confining conductive bump materi...
- Patent number 9,679,811
- Issue date Jun 13, 2017
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming bond-on-lead interconnec...
- Patent number 9,679,824
- Issue date Jun 13, 2017
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip interconnect solder mask
- Patent number 9,545,014
- Issue date Jan 10, 2017
- STATS ChipPAC Pte. Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
HIGH-DENSITY SYSTEM-ON-CHIP PARTITIONING
- Publication number 20240332252
- Publication date Oct 3, 2024
- Meta Platforms Technologies, LLC
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES FOR DIFFERENTIATED ARTIFICIAL-REALITY TASK-SP...
- Publication number 20240332260
- Publication date Oct 3, 2024
- Meta Platforms Technologies, LLC
- Sunil Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D INTEGRATED IN-PACKAGE MAIN MEMORY
- Publication number 20240332275
- Publication date Oct 3, 2024
- Meta Platforms Technologies, LLC
- Jaesik Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIVERSAL CHIP WITH VARIABLE PACKAGING
- Publication number 20240312892
- Publication date Sep 19, 2024
- Meta Platforms Technologies, LLC
- Rajendra D. PENDSE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D CHIPLET INTEGRATION USING FAN-OUT WAFER-LEVEL PACKAGING
- Publication number 20240274587
- Publication date Aug 15, 2024
- Meta Platforms Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED TIME-OF-FLIGHT MODULE
- Publication number 20240241231
- Publication date Jul 18, 2024
- Meta Platforms Technologies, LLC
- Jack Diepen Mumbo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARTIFICIAL REALITY SYSTEM HAVING SYSTEM-ON-A-CHIP (SoC) INTEGRATED...
- Publication number 20230094261
- Publication date Mar 30, 2023
- Meta Platforms Technologies, LLC
- Rajendra D. Pendse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEFT AND RIGHT PROJECTORS FOR DISPLAY DEVICE
- Publication number 20230034214
- Publication date Feb 2, 2023
- Meta Platforms Technologies, LLC
- Rajendra D. PENDSE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAMERA MODULE WITH COMPONENT SIZE BASED ON IMAGE SENSOR
- Publication number 20220407987
- Publication date Dec 22, 2022
- Meta Platforms Technologies, LLC
- Chao Han
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SEMICONDUCTOR RECONSTITUTION
- Publication number 20220328740
- Publication date Oct 13, 2022
- Facebook Technologies, LLC
- Rajendra D. PENDSE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MANAGING THERMAL RESISTANCE AND PLANARITY OF A DISPLAY PACKAGE
- Publication number 20220285601
- Publication date Sep 8, 2022
- Facebook Technologies, LLC
- Rajendra D. PENDSE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALIGNING A COLLIMATOR ASSEMBLY WITH LED ARRAYS
- Publication number 20220229301
- Publication date Jul 21, 2022
- Facebook Technologies, LLC
- Rajendra D. PENDSE
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
ARTIFICIAL REALITY SYSTEM HAVING SYSTEM-ON-A-CHIP (SoC) INTEGRATED...
- Publication number 20210405382
- Publication date Dec 30, 2021
- Facebook Technologies, LLC
- Rajendra D. PENDSE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED DISPLAY DEVICES
- Publication number 20210335767
- Publication date Oct 28, 2021
- Facebook Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING CONTROL CIRCUITS WITH LIGHT EMISSIVE CIRCUITS WITH DISS...
- Publication number 20210288036
- Publication date Sep 16, 2021
- Facebook Technologies, LLC
- Rajendra D. PENDSE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING CONTROL CIRCUITS WITH LIGHT EMISSIVE CIRCUITS WITH DISS...
- Publication number 20210288032
- Publication date Sep 16, 2021
- Facebook Technologies, LLC
- Rajendra D. PENDSE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEFT AND RIGHT PROJECTORS FOR DISPLAY DEVICE
- Publication number 20210175216
- Publication date Jun 10, 2021
- Facebook Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALIGNING A COLLIMATOR ASSEMBLY WITH LED ARRAYS
- Publication number 20210165318
- Publication date Jun 3, 2021
- Facebook Technologies, LLC
- Rajendra D. PENDSE
- G02 - OPTICS
Information Patent Application
MANAGING THERMAL RESISTANCE AND PLANARITY OF A DISPLAY PACKAGE
- Publication number 20210167268
- Publication date Jun 3, 2021
- Facebook Technologies, LLC
- Rajendra D. PENDSE
- G02 - OPTICS
Information Patent Application
REDUCING THE PLANARITY VARIATION IN A DISPLAY DEVICE
- Publication number 20210013099
- Publication date Jan 14, 2021
- Facebook Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application...
- Publication number 20200279827
- Publication date Sep 3, 2020
- STATS ChipPAC Pte Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED DISPLAY DEVICES
- Publication number 20200266180
- Publication date Aug 20, 2020
- Facebook Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKING OF THREE-DIMENSIONAL CIRCUITS INCLUDING THROUGH-SILICON-VIAS
- Publication number 20200098729
- Publication date Mar 26, 2020
- Facebook Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application...
- Publication number 20180096963
- Publication date Apr 5, 2018
- STATS ChipPAC Pte Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Electromagnetic (EM) Shi...
- Publication number 20170330840
- Publication date Nov 16, 2017
- STATS ChipPAC Pte Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ON PACKAGE (PoP) DEVICE COMPRISING THERMAL INTERFACE MATERI...
- Publication number 20170294422
- Publication date Oct 12, 2017
- QUALCOMM Incorporated
- Michael James Solimando
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EXPOSED DIE MOLD UNDERFILL (MUF) WITH FINE PITCH COPPER (CU) PILLAR...
- Publication number 20170271175
- Publication date Sep 21, 2017
- QUALCOMM Incorporated
- Christopher James HEALY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Package with Embedded Die
- Publication number 20160284619
- Publication date Sep 29, 2016
- STATS ChipPAC Pte Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Self-Confinement of Conductive B...
- Publication number 20160260646
- Publication date Sep 8, 2016
- STATS ChipPAC Pte Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Self-Confinement of Conductive B...
- Publication number 20160071813
- Publication date Mar 10, 2016
- STATS ChipPAC, Ltd.
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS

Rajendra D. Pendse

Person

Patents Grantslast 30 patents

Integrating control circuits with light emissive circuits with diss...

Managing thermal resistance and planarity of a display package

Artificial reality system having system-on-a-chip (soc) integrated...

Integrating control circuits with light emissive circuits with diss...

Aligning a collimator assembly with LED arrays

Artificial reality system having system-on-a-chip (SoC) integrated...

Integrated display devices

Left and right projectors for display device

Managing thermal resistance and planarity of a display package

Aligning a collimator assembly with LED arrays

Thin 3D fan-out embedded wafer level package (EWLB) for application...

Integrated display devices

Stacking of three-dimensional circuits including through-silicon-vias

Thin 3D fan-out embedded wafer level package (EWLB) for application...

Semiconductor device and method of forming high routing density int...

Semiconductor device and method of forming electrical interconnect...

Semiconductor device and method of forming flipchip interconnect st...

Semiconductor device and method of forming electromagnetic (EM) shi...

Package on package (PoP) device comprising thermal interface materi...

Bump-on-lead flip chip interconnection

Semiconductor device and method of self-confinement of conductive b...

Thin 3D fan-out embedded wafer level package (EWLB) for application...

Semiconductor device and method of self-confinement of conductive b...

Semiconductor device and method of forming vertical interconnect st...

Semiconductor device and method of forming pad layout for flipchip...

Solder joint flip chip interconnection having relief structure

Semiconductor device and method of forming electromagnetic (EM) shi...

Semiconductor device and method of confining conductive bump materi...

Semiconductor device and method of forming bond-on-lead interconnec...

Flip chip interconnect solder mask

Patents Applicationslast 30 patents

HIGH-DENSITY SYSTEM-ON-CHIP PARTITIONING

PACKAGE ARCHITECTURES FOR DIFFERENTIATED ARTIFICIAL-REALITY TASK-SP...

3D INTEGRATED IN-PACKAGE MAIN MEMORY

UNIVERSAL CHIP WITH VARIABLE PACKAGING

3D CHIPLET INTEGRATION USING FAN-OUT WAFER-LEVEL PACKAGING

STACKED TIME-OF-FLIGHT MODULE

ARTIFICIAL REALITY SYSTEM HAVING SYSTEM-ON-A-CHIP (SoC) INTEGRATED...

LEFT AND RIGHT PROJECTORS FOR DISPLAY DEVICE

CAMERA MODULE WITH COMPONENT SIZE BASED ON IMAGE SENSOR

SEMICONDUCTOR RECONSTITUTION

MANAGING THERMAL RESISTANCE AND PLANARITY OF A DISPLAY PACKAGE

ALIGNING A COLLIMATOR ASSEMBLY WITH LED ARRAYS

ARTIFICIAL REALITY SYSTEM HAVING SYSTEM-ON-A-CHIP (SoC) INTEGRATED...

INTEGRATED DISPLAY DEVICES

INTEGRATING CONTROL CIRCUITS WITH LIGHT EMISSIVE CIRCUITS WITH DISS...

INTEGRATING CONTROL CIRCUITS WITH LIGHT EMISSIVE CIRCUITS WITH DISS...

LEFT AND RIGHT PROJECTORS FOR DISPLAY DEVICE

ALIGNING A COLLIMATOR ASSEMBLY WITH LED ARRAYS

MANAGING THERMAL RESISTANCE AND PLANARITY OF A DISPLAY PACKAGE

REDUCING THE PLANARITY VARIATION IN A DISPLAY DEVICE

Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application...

INTEGRATED DISPLAY DEVICES

STACKING OF THREE-DIMENSIONAL CIRCUITS INCLUDING THROUGH-SILICON-VIAS

Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application...

Semiconductor Device and Method of Forming Electromagnetic (EM) Shi...

PACKAGE ON PACKAGE (PoP) DEVICE COMPRISING THERMAL INTERFACE MATERI...

EXPOSED DIE MOLD UNDERFILL (MUF) WITH FINE PITCH COPPER (CU) PILLAR...

Semiconductor Package with Embedded Die

Semiconductor Device and Method of Self-Confinement of Conductive B...

Semiconductor Device and Method of Self-Confinement of Conductive B...