Rajesh Tiwari

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Continuous write and read operations for memories with latencies
- Patent number 9,972,402
- Issue date May 15, 2018
- QUALCOMM Incorporated
- Nishi Bhushan Singh
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for multiple memory shared collar architecture
- Patent number 9,971,663
- Issue date May 15, 2018
- QUALCOMM Incorporated
- Nishi Bhushan Singh
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan compression architecture with bypassable scan chains for low t...
- Patent number 8,856,601
- Issue date Oct 7, 2014
- Texas Instruments Incorporated
- Srivaths Ravi
- G01 - MEASURING TESTING
Information Patent Grant
Enhanced control in scan tests of integrated circuits with partitio...
- Patent number 8,205,125
- Issue date Jun 19, 2012
- Texas Instruments Incorporated
- Alan David Hales
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-LEVEL CLOCK GATE CONTROLS TO ADDRESS SCAN MODE POWER DROOP AN...
- Publication number 20180019733
- Publication date Jan 18, 2018
- QUALCOMM Incorporated
- Rajesh Tiwari
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CONTINUOUS WRITE AND READ OPERATIONS FOR MEMORIES WITH LATENCIES
- Publication number 20170309348
- Publication date Oct 26, 2017
- QUALCOMM Incorporated
- Nishi Bhushan Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY CONFIGURABLE SHARED SCAN CLOCK CHANNEL ARCHITECTURE
- Publication number 20170184665
- Publication date Jun 29, 2017
- QUALCOMM Incorporated
- Rajesh Tiwari
- G01 - MEASURING TESTING
Information Patent Application
ENHANCED MEMORY BUILT-IN SELF-TEST ARCHITECTURE FOR DE-FEATURED MEM...
- Publication number 20170110204
- Publication date Apr 20, 2017
- QUALCOMM Incorporated
- Abhinav Kothiala
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR MULTIPLE MEMORY SHARED COLLAR ARCHITECTURE
- Publication number 20160062864
- Publication date Mar 3, 2016
- QUALCOMM Incorporated
- Nishi Bhushan Singh
- G01 - MEASURING TESTING
Information Patent Application
SCAN PROGRAMMABLE REGISTER CONTROLLED CLOCK ARCHITECTURE FOR TESTIN...
- Publication number 20160061892
- Publication date Mar 3, 2016
- QUALCOMM Incorporated
- Rajesh Tiwari
- G01 - MEASURING TESTING
Information Patent Application
TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION
- Publication number 20150212152
- Publication date Jul 30, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Khushboo Agarwal
- G01 - MEASURING TESTING
Information Patent Application
Scan Compression Architecture with Bypassable Scan Chains for Low T...
- Publication number 20130159800
- Publication date Jun 20, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Srivaths Ravi
- G01 - MEASURING TESTING
Information Patent Application
ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIO...
- Publication number 20110099442
- Publication date Apr 28, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Alan David Hales
- G01 - MEASURING TESTING

Rajesh Tiwari

Person

Patents Grantslast 30 patents

Continuous write and read operations for memories with latencies

Method and apparatus for multiple memory shared collar architecture

Scan compression architecture with bypassable scan chains for low t...

Enhanced control in scan tests of integrated circuits with partitio...

Patents Applicationslast 30 patents

MULTI-LEVEL CLOCK GATE CONTROLS TO ADDRESS SCAN MODE POWER DROOP AN...

CONTINUOUS WRITE AND READ OPERATIONS FOR MEMORIES WITH LATENCIES

DYNAMICALLY CONFIGURABLE SHARED SCAN CLOCK CHANNEL ARCHITECTURE

ENHANCED MEMORY BUILT-IN SELF-TEST ARCHITECTURE FOR DE-FEATURED MEM...

METHOD AND APPARATUS FOR MULTIPLE MEMORY SHARED COLLAR ARCHITECTURE

SCAN PROGRAMMABLE REGISTER CONTROLLED CLOCK ARCHITECTURE FOR TESTIN...

TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION

Scan Compression Architecture with Bypassable Scan Chains for Low T...

ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIO...