Rajiv Kumar

Person

Penang, MY

People

Patents Grantslast 30 patents

Information Patent Grant
Memory read circuit with N type and P type pre-charge
- Patent number 10,497,405
- Issue date Dec 3, 2019
- Intel Corporation
- Rajiv Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for reducing power consumption in memory circ...
- Patent number 10,431,269
- Issue date Oct 1, 2019
- Altera Corporation
- Rajiv Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element write-assist circuitry with dummy bit lines
- Patent number 10,236,055
- Issue date Mar 19, 2019
- Altera Corporation
- Rajiv Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for security in an integrated circuit
- Patent number 10,228,415
- Issue date Mar 12, 2019
- Altera Corporation
- Wei Yee Koay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory elements with dynamic pull-up weakening write assist circuitry
- Patent number 9,767,892
- Issue date Sep 19, 2017
- Altera Corporation
- Rajiv Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration bit architecture for programmable integrated circuit...
- Patent number 9,219,067
- Issue date Dec 22, 2015
- Altera Corporation
- Rajiv Kumar
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Systems And Methods For Communication Between Integrated Circuits U...
- Publication number 20250225092
- Publication date Jul 10, 2025
- Altera Corporation
- Scott Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuits And Methods For Memory Built-In-Self-Tests
- Publication number 20240412799
- Publication date Dec 12, 2024
- Altera Corporation
- Kok Wah Khor
- G11 - INFORMATION STORAGE
Information Patent Application
Configurable Storage Circuits And Methods
- Publication number 20240337692
- Publication date Oct 10, 2024
- Intel Corporation
- Rajiv Kumar
- G01 - MEASURING TESTING
Information Patent Application
Techniques For Accessing Memory Circuits
- Publication number 20230131938
- Publication date Apr 27, 2023
- Intel Corporation
- Scott Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FABRIC MEMORY NETWORK-ON-CHIP
- Publication number 20220221986
- Publication date Jul 14, 2022
- Scott Jeremy Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable High-Speed and Low-power Mode FPGA Memory with Configu...
- Publication number 20190228821
- Publication date Jul 25, 2019
- Intel Corporation
- Wei Yee Koay
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY READ CIRCUIT WITH N TYPE AND P TYPE PRE-CHARGE
- Publication number 20190103140
- Publication date Apr 4, 2019
- Intel Corporation
- Rajiv KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR REDUCING POWER CONSUMPTION IN MEMORY CIRC...
- Publication number 20160225437
- Publication date Aug 4, 2016
- Altera Corporation
- Rajiv Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURATION BIT ARCHITECTURE FOR PROGRAMMABLE INTEGRATED CIRCUIT...
- Publication number 20150214229
- Publication date Jul 30, 2015
- Altera Corporation
- Rajiv Kumar
- H01 - BASIC ELECTRIC ELEMENTS

Rajiv Kumar

Person

Patents Grantslast 30 patents

Memory read circuit with N type and P type pre-charge

Methods and apparatus for reducing power consumption in memory circ...

Memory element write-assist circuitry with dummy bit lines

Apparatus and method for security in an integrated circuit

Memory elements with dynamic pull-up weakening write assist circuitry

Configuration bit architecture for programmable integrated circuit...

Patents Applicationslast 30 patents

Systems And Methods For Communication Between Integrated Circuits U...

Circuits And Methods For Memory Built-In-Self-Tests

Configurable Storage Circuits And Methods

Techniques For Accessing Memory Circuits

FABRIC MEMORY NETWORK-ON-CHIP

Programmable High-Speed and Low-power Mode FPGA Memory with Configu...

MEMORY READ CIRCUIT WITH N TYPE AND P TYPE PRE-CHARGE

METHODS AND APPARATUS FOR REDUCING POWER CONSUMPTION IN MEMORY CIRC...

CONFIGURATION BIT ARCHITECTURE FOR PROGRAMMABLE INTEGRATED CIRCUIT...