Ralph Sanchez

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Amity, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Field triage of EOS failures in semiconductor devices
- Patent number 9,939,488
- Issue date Apr 10, 2018
- Teseda Corporation
- Joseph M. Salazar
- G01 - MEASURING TESTING
Information Patent Grant
Suspect logical region synthesis from device design and test inform...
- Patent number 9,659,136
- Issue date May 23, 2017
- Teseda Corporation
- Armagan Akar
- G11 - INFORMATION STORAGE
Information Patent Grant
Correlation of device manufacturing defect data with device electri...
- Patent number 8,918,753
- Issue date Dec 23, 2014
- Teseda Corporation
- Armagan Akar
- G11 - INFORMATION STORAGE
Information Patent Grant
Secure test-for-yield chip diagnostics management system and method
- Patent number 8,626,460
- Issue date Jan 7, 2014
- Teseda Corporation
- Bruce Kaufman
- G01 - MEASURING TESTING
Information Patent Grant
Correlation of device manufacturing defect data with device electri...
- Patent number 8,539,389
- Issue date Sep 17, 2013
- Teseda Corporation
- Armagan Akar
- G11 - INFORMATION STORAGE
Information Patent Grant
Suspect logical region synthesis and simulation using device design...
- Patent number 8,453,088
- Issue date May 28, 2013
- Teseda Corporation
- Armagan Akar
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
FIELD TRIAGE OF EOS FAILURES IN SEMICONDUCTOR DEVICES
- Publication number 20150149106
- Publication date May 28, 2015
- TESEDA CORPORATION
- Joseph M. Salazar
- G01 - MEASURING TESTING
Information Patent Application
Correlation of Device Manufacturing Defect Data with Device Electri...
- Publication number 20140115551
- Publication date Apr 24, 2014
- TESEDA CORPORATION
- Armagan Akar
- G01 - MEASURING TESTING
Information Patent Application
SUSPECT LOGICAL REGION SYNTHESIS FROM DEVICE DESIGN AND TEST INFORM...
- Publication number 20120079439
- Publication date Mar 29, 2012
- TESEDA CORPORATION
- Armagan Akar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUSPECT LOGICAL REGION SYNTHESIS AND SIMULATION USING DEVICE DESIGN...
- Publication number 20120079440
- Publication date Mar 29, 2012
- TESEDA CORPORATION
- Armagan Akar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CORRELATION OF DEVICE MANUFACTURING DEFECT DATA WITH DEVICE ELECTRI...
- Publication number 20120079442
- Publication date Mar 29, 2012
- TESEDA CORPORATION
- Armagan Akar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure test-for-yield chip diagnostics management system and method
- Publication number 20100332172
- Publication date Dec 30, 2010
- Bruce Kaufman
- G01 - MEASURING TESTING