Raman S. Thiara

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and architectures for secure ranging
- Patent number 12,089,178
- Issue date Sep 10, 2024
- Apple Inc.
- Jerrold V. Hauck
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and architectures for secure ranging
- Patent number 11,818,681
- Issue date Nov 14, 2023
- Apple Inc.
- Jerrold V. Hauck
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Electronic device functionality in low power mode
- Patent number 11,693,467
- Issue date Jul 4, 2023
- Apple Inc.
- Langford M. Wasada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and architectures for secure ranging
- Patent number 11,265,929
- Issue date Mar 1, 2022
- Apple Inc.
- Jerrold V. Hauck
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Mitigation of power supply disturbance for wired-line transmitters
- Patent number 9,715,262
- Issue date Jul 25, 2017
- Apple Inc.
- Wenbo Liu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for power glitch detection in integrated circuits
- Patent number 9,541,603
- Issue date Jan 10, 2017
- Apple Inc.
- Brian S. Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital-to-analog converter system
- Patent number 9,374,103
- Issue date Jun 21, 2016
- Apple Inc.
- Wenbo Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock divider circuit with synchronized switching
- Patent number 9,306,574
- Issue date Apr 5, 2016
- Apple Inc.
- Feng Zhao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Link clock change during veritcal blanking
- Patent number 9,158,350
- Issue date Oct 13, 2015
- Apple Inc.
- Brijesh Tripathi
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Low power display port with arbitrary link clock frequency
- Patent number 9,013,493
- Issue date Apr 21, 2015
- Apple Inc.
- Brijesh Tripathi
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Clock generation using fixed dividers and multiplex circuits
- Patent number 8,963,587
- Issue date Feb 24, 2015
- Apple Inc.
- Erik P. Machnicki
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND ARCHITECTURES FOR SECURE RANGING
- Publication number 20240049165
- Publication date Feb 8, 2024
- Apple Inc.
- Jerrold V. HAUCK
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ELECTRONIC DEVICE FUNCTIONALITY IN LOW POWER MODE
- Publication number 20230061200
- Publication date Mar 2, 2023
- Apple Inc.
- Langford M. Wasada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND ARCHITECTURES FOR SECURE RANGING
- Publication number 20220225267
- Publication date Jul 14, 2022
- Apple Inc.
- Jerrold V. HAUCK
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHODS AND ARCHITECTURES FOR SECURE RANGING
- Publication number 20190116619
- Publication date Apr 18, 2019
- Apple Inc.
- Jerrold V. HAUCK
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MITIGATION OF POWER SUPPLY DISTURBANCE FOR WIRED-LINE TRANSMITTERS
- Publication number 20160062430
- Publication date Mar 3, 2016
- Apple Inc.
- Wenbo Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Power Glitch Detection in Integrated Circuits
- Publication number 20150015283
- Publication date Jan 15, 2015
- Apple Inc.
- Brian S. Park
- G01 - MEASURING TESTING
Information Patent Application
Clock Generation Using Fixed Dividers and Multiplex Circuits
- Publication number 20140340130
- Publication date Nov 20, 2014
- Apple Inc.
- Erik P. Machnicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER DISPLAY PORT WITH ARBITRARY LINK CLOCK FREQUENCY
- Publication number 20140168234
- Publication date Jun 19, 2014
- Apple Inc.
- Brijesh Tripathi
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
LINK CLOCK CHANGE DURING VERITCAL BLANKING
- Publication number 20140173313
- Publication date Jun 19, 2014
- Apple Inc.
- Brijesh Tripathi
- G06 - COMPUTING CALCULATING COUNTING

Raman S. Thiara

Person

Patents Grantslast 30 patents

Methods and architectures for secure ranging

Methods and architectures for secure ranging

Electronic device functionality in low power mode

Methods and architectures for secure ranging

Mitigation of power supply disturbance for wired-line transmitters

Method and apparatus for power glitch detection in integrated circuits

Digital-to-analog converter system

Clock divider circuit with synchronized switching

Link clock change during veritcal blanking

Low power display port with arbitrary link clock frequency

Clock generation using fixed dividers and multiplex circuits

Patents Applicationslast 30 patents

METHODS AND ARCHITECTURES FOR SECURE RANGING

ELECTRONIC DEVICE FUNCTIONALITY IN LOW POWER MODE

METHODS AND ARCHITECTURES FOR SECURE RANGING

METHODS AND ARCHITECTURES FOR SECURE RANGING

MITIGATION OF POWER SUPPLY DISTURBANCE FOR WIRED-LINE TRANSMITTERS

Method and Apparatus for Power Glitch Detection in Integrated Circuits

Clock Generation Using Fixed Dividers and Multiplex Circuits

LOW POWER DISPLAY PORT WITH ARBITRARY LINK CLOCK FREQUENCY

LINK CLOCK CHANGE DURING VERITCAL BLANKING