Ramnath Venkatraman

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Closed-loop adaptive voltage scaling for integrated circuits
- Patent number 9,158,319
- Issue date Oct 13, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Manjunatha Gowda
- G05 - CONTROLLING REGULATING
Information Patent Grant
Power controller for SoC power gating applications
- Patent number 8,738,940
- Issue date May 27, 2014
- LSI Corporation
- Ramnath Venkatraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mitigation of detrimental breakdown of a high dielectric constant m...
- Patent number 8,624,352
- Issue date Jan 7, 2014
- LSI Corporation
- Bonnie E. Weir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Total power optimization for a logic integrated circuit
- Patent number 8,589,853
- Issue date Nov 19, 2013
- LSI Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Basic cell architecture for structured ASICs
- Patent number 8,429,586
- Issue date Apr 23, 2013
- LSI Corporation
- Ramnath Venkatraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Defectivity-immune technique of implementing MIM-based decoupling c...
- Patent number 8,411,399
- Issue date Apr 2, 2013
- LSI Corporation
- Ramnath Venkatraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit cell architecture configurable for memory or log...
- Patent number 8,178,909
- Issue date May 15, 2012
- LSI Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Basic cell architecture for structured application-specific integra...
- Patent number 8,166,440
- Issue date Apr 24, 2012
- LSI Corporation
- Ramnath Venkatraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimization with adaptive body biasing
- Patent number 8,112,734
- Issue date Feb 7, 2012
- LSI Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit cell architecture configurable for memory or log...
- Patent number 8,044,437
- Issue date Oct 25, 2011
- LSI Logic Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM based one-time-programmable memory
- Patent number 7,869,251
- Issue date Jan 11, 2011
- LSI Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Modular design of multiport memory bitcells
- Patent number 7,440,356
- Issue date Oct 21, 2008
- LSI Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Basic cell architecture for structured application-specific integra...
- Patent number 7,404,154
- Issue date Jul 22, 2008
- LSI Corporation
- Ramnath Venkatraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compact ternary and binary CAM bitcell architecture with no enclose...
- Patent number 7,304,874
- Issue date Dec 4, 2007
- LSI Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for verifying the write speed of SRAM cells
- Patent number 7,082,067
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Optical proximity correction method using weighted priorities
- Patent number 7,069,535
- Issue date Jun 27, 2006
- LSI Logic Corporation
- Olga A. Kobozeva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ternary CAM bitcells
- Patent number 7,042,747
- Issue date May 9, 2006
- LSI Logic Corporation
- Ruggero Castagnetti
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell architecture
- Patent number 7,006,370
- Issue date Feb 28, 2006
- LSI Logic Corporation
- Subramanian Ramesh
- G11 - INFORMATION STORAGE
Information Patent Grant
Design and use of a spacer cell to support reconfigurable memories
- Patent number 7,006,369
- Issue date Feb 28, 2006
- LSI Logic Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell architecture for reduced routing congestion
- Patent number 6,980,462
- Issue date Dec 27, 2005
- LSI Logic Corporation
- Subramanian Ramesh
- G11 - INFORMATION STORAGE
Information Patent Grant
Reconfigurable memory arrays
- Patent number 6,934,174
- Issue date Aug 23, 2005
- LSI Logic Corporation
- Ruggero Castagnetti
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of forming metal fuses in CMOS processes with copper interco...
- Patent number 6,828,653
- Issue date Dec 7, 2004
- LSI Logic Corporation
- Ruggero Castagnetti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fuse construction for integrated circuit structure having low diele...
- Patent number 6,806,551
- Issue date Oct 19, 2004
- LSI Logic Corporation
- Yauh-Ching Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming metal fuses in CMOS processes with copper interco...
- Patent number 6,664,141
- Issue date Dec 16, 2003
- LSI Logic Corporation
- Ruggero Castagnetti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fuse construction for integrated circuit structure having low diele...
- Patent number 6,566,171
- Issue date May 20, 2003
- LSI Logic Corporation
- Yauh-Ching Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single channel four transistor SRAM
- Patent number 6,442,061
- Issue date Aug 27, 2002
- LSI Logic Corporation
- Weiran Kong
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CLOSED-LOOP ADAPTIVE VOLTAGE SCALING FOR INTEGRATED CIRCUITS
- Publication number 20150109052
- Publication date Apr 23, 2015
- LSI Corporation
- Manjunatha Gowda
- G05 - CONTROLLING REGULATING
Information Patent Application
TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT
- Publication number 20140040842
- Publication date Feb 6, 2014
- LSI Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICAL PATH MONITOR HARDWARE ARCHITECTURE FOR CLOSED LOOP ADAPTI...
- Publication number 20140028364
- Publication date Jan 30, 2014
- LSI Corporation
- Ramnath Venkatraman
- G01 - MEASURING TESTING
Information Patent Application
REDUCING POWER CONSUMPTION OF MEMORY
- Publication number 20130166930
- Publication date Jun 27, 2013
- LSI CORPORATION
- Ting Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING POWER CONSUMPTION OF MEMORY
- Publication number 20130166931
- Publication date Jun 27, 2013
- LSI CORPORATION
- Ruggero Castagnetti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTE...
- Publication number 20130154109
- Publication date Jun 20, 2013
- LSI Corporation
- Ramnath Venkatraman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER CONTROLLER FOR SOC POWER GATING APPLICATIONS
- Publication number 20130057338
- Publication date Mar 7, 2013
- LSI Corporation
- Ramnath Venkatraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT
- Publication number 20120290994
- Publication date Nov 15, 2012
- LSI Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Basic Cell Architecture For Structured ASICs
- Publication number 20120175683
- Publication date Jul 12, 2012
- LSI Corporation
- Ramnath Venkatraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATION OF DETRIMENTAL BREAKDOWN OF A HIGH DIELECTRIC CONSTANT M...
- Publication number 20120126364
- Publication date May 24, 2012
- LSI Corporation
- Bonnie E. Weir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Cell Architecture Configurable for Memory or Log...
- Publication number 20120012896
- Publication date Jan 19, 2012
- Ramnath Venkatraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DEFECTIVITY-IMMUNE TECHNIQUE OF IMPLEMENTING MIM-BASED DECOUPLING C...
- Publication number 20110051304
- Publication date Mar 3, 2011
- LSI Corporation
- Ramnath Venkatraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SRAM BASED ONE-TIME-PROGRAMMABLE MEMORY
- Publication number 20100080035
- Publication date Apr 1, 2010
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Application
DESIGN OPTIMIZATION WITH ADAPTIVE BODY BIASING
- Publication number 20100083193
- Publication date Apr 1, 2010
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modular design of multiport memory bitcells
- Publication number 20080013383
- Publication date Jan 17, 2008
- LSI Logic Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Application
Compact ternary and binary CAM bitcell architecture with no enclose...
- Publication number 20060203530
- Publication date Sep 14, 2006
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit for verifying the write speed of SRAM cells
- Publication number 20060050600
- Publication date Mar 9, 2006
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Application
Reconfigurable memory arrays
- Publication number 20050047238
- Publication date Mar 3, 2005
- Ruggero Castagnetti
- G11 - INFORMATION STORAGE
Information Patent Application
Design and use of a spacer cell to support reconfigurable memories
- Publication number 20050047254
- Publication date Mar 3, 2005
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Application
Optical proximity correction method using weighted priorities
- Publication number 20040250232
- Publication date Dec 9, 2004
- Olga A. Kobozeva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fuse construction for integrated circuit structure having low diele...
- Publication number 20030164532
- Publication date Sep 4, 2003
- Yauh-Ching Liu
- H01 - BASIC ELECTRIC ELEMENTS

Ramnath Venkatraman

Person

Patents Grantslast 30 patents

Closed-loop adaptive voltage scaling for integrated circuits

Power controller for SoC power gating applications

Mitigation of detrimental breakdown of a high dielectric constant m...

Total power optimization for a logic integrated circuit

Basic cell architecture for structured ASICs

Defectivity-immune technique of implementing MIM-based decoupling c...

Integrated circuit cell architecture configurable for memory or log...

Basic cell architecture for structured application-specific integra...

Optimization with adaptive body biasing

Integrated circuit cell architecture configurable for memory or log...

SRAM based one-time-programmable memory

Modular design of multiport memory bitcells

Basic cell architecture for structured application-specific integra...

Compact ternary and binary CAM bitcell architecture with no enclose...

Circuit for verifying the write speed of SRAM cells

Optical proximity correction method using weighted priorities

Ternary CAM bitcells

Memory cell architecture

Design and use of a spacer cell to support reconfigurable memories

Memory cell architecture for reduced routing congestion

Reconfigurable memory arrays

Method of forming metal fuses in CMOS processes with copper interco...

Fuse construction for integrated circuit structure having low diele...

Method of forming metal fuses in CMOS processes with copper interco...

Fuse construction for integrated circuit structure having low diele...

Single channel four transistor SRAM

Patents Applicationslast 30 patents

CLOSED-LOOP ADAPTIVE VOLTAGE SCALING FOR INTEGRATED CIRCUITS

TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT

CRITICAL PATH MONITOR HARDWARE ARCHITECTURE FOR CLOSED LOOP ADAPTI...

REDUCING POWER CONSUMPTION OF MEMORY

REDUCING POWER CONSUMPTION OF MEMORY

METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTE...

POWER CONTROLLER FOR SOC POWER GATING APPLICATIONS

TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT

Basic Cell Architecture For Structured ASICs

MITIGATION OF DETRIMENTAL BREAKDOWN OF A HIGH DIELECTRIC CONSTANT M...

Integrated Circuit Cell Architecture Configurable for Memory or Log...

DEFECTIVITY-IMMUNE TECHNIQUE OF IMPLEMENTING MIM-BASED DECOUPLING C...

SRAM BASED ONE-TIME-PROGRAMMABLE MEMORY

DESIGN OPTIMIZATION WITH ADAPTIVE BODY BIASING

Modular design of multiport memory bitcells

Compact ternary and binary CAM bitcell architecture with no enclose...

Circuit for verifying the write speed of SRAM cells

Reconfigurable memory arrays

Design and use of a spacer cell to support reconfigurable memories

Optical proximity correction method using weighted priorities

Fuse construction for integrated circuit structure having low diele...