Ranko Scepanovic

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Architectural floorplan for a structured ASIC manufactured on a 28...
- Patent number 9,024,657
- Issue date May 5, 2015
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Via-configurable high-performance logic block involving transistor...
- Patent number 8,957,398
- Issue date Feb 17, 2015
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data shredding RAID mode
- Patent number 8,806,227
- Issue date Aug 12, 2014
- LSI Corporation
- Mikhail I. Grinchuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Via-configurable high-performance logic block architecture
- Patent number 8,735,857
- Issue date May 27, 2014
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for generating memory models and timing database
- Patent number 8,566,769
- Issue date Oct 22, 2013
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and computer program for generating grounded shielding wires...
- Patent number 8,516,425
- Issue date Aug 20, 2013
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating memory models and timing database
- Patent number 8,245,168
- Issue date Aug 14, 2012
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for balancing signal delay skew
- Patent number 8,239,813
- Issue date Aug 7, 2012
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory mapping for parallel turbo decoding
- Patent number 8,132,075
- Issue date Mar 6, 2012
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for mapping design memories to integrated circ...
- Patent number 8,037,432
- Issue date Oct 11, 2011
- LSI Corporation
- Alexandre Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for programmable decoding of a plurality of c...
- Patent number 8,035,537
- Issue date Oct 11, 2011
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for outputting a sequence of commands and data de...
- Patent number 8,006,209
- Issue date Aug 23, 2011
- LSI Corporation
- Andrey A. Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal delay skew reduction system
- Patent number 7,996,804
- Issue date Aug 9, 2011
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decision tree representation of a function
- Patent number 7,877,724
- Issue date Jan 25, 2011
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Command language for memory testing
- Patent number 7,856,577
- Issue date Dec 21, 2010
- LSI Corporation
- Alexander E. Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Generation of test sequences during memory built-in self testing of...
- Patent number 7,788,563
- Issue date Aug 31, 2010
- LSI Corporation
- Alexandre E. Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance tiling for RRAM memory
- Patent number 7,739,471
- Issue date Jun 15, 2010
- LSI Corporation
- Alexander Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipelined LDPC arithmetic unit
- Patent number 7,739,575
- Issue date Jun 15, 2010
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for generating memory models and timing database
- Patent number 7,584,442
- Issue date Sep 1, 2009
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multimode delay analysis for simplifying integrated circuit design...
- Patent number 7,512,918
- Issue date Mar 31, 2009
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for outputting a sequence of commands and data de...
- Patent number 7,472,358
- Issue date Dec 30, 2008
- LSI Corporation
- Andrey A. Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for mapping design memories to integrated circ...
- Patent number 7,424,687
- Issue date Sep 9, 2008
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory timing model with back-annotating
- Patent number 7,415,686
- Issue date Aug 19, 2008
- LSI Corporation
- Alexander Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for outputting a sequence of commands and data de...
- Patent number 7,415,691
- Issue date Aug 19, 2008
- LSI Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for tiling memories in integrated circuit layout
- Patent number 7,389,484
- Issue date Jun 17, 2008
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for analyzing the quality of an OPC mask
- Patent number 7,340,706
- Issue date Mar 4, 2008
- LSI Logic Corporation
- Ilya Golubtsov
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Verification of RRAM tiling netlist
- Patent number 7,315,993
- Issue date Jan 1, 2008
- LSI Logic Corporation
- Andrey A. Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory mapping for parallel turbo decoding
- Patent number 7,305,593
- Issue date Dec 4, 2007
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for efficiently testing a large random access mem...
- Patent number 7,305,597
- Issue date Dec 4, 2007
- LSI Corporation
- Alexander E. Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Search engine for large-width data
- Patent number 7,231,383
- Issue date Jun 12, 2007
- LSI Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
STRUCTURED INTEGRATED CIRCUIT DEVICE WITH MULTIPLE CONFIGURABLE VIA...
- Publication number 20160293541
- Publication date Oct 6, 2016
- eASIC Corporation
- Alexander ANDREEV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Architectural Floorplan for a Structured ASIC Manufactured on a 28...
- Publication number 20140103959
- Publication date Apr 17, 2014
- eASIC Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Via-Configurable High-Performance Logic Block Involving Transistor...
- Publication number 20140028348
- Publication date Jan 30, 2014
- eASIC Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Generating Memory Models and Timing Database
- Publication number 20120278775
- Publication date Nov 1, 2012
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20120278783
- Publication date Nov 1, 2012
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Via-Configurable High-Performance Logic Block Architecture
- Publication number 20120161093
- Publication date Jun 28, 2012
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20110258587
- Publication date Oct 20, 2011
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Generating Memory Models and Timing Database
- Publication number 20100023904
- Publication date Jan 28, 2010
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generation Of Test Sequences During Memory Built-In Self Testing Of...
- Publication number 20090316507
- Publication date Dec 24, 2009
- Alexandre E. Andreev
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR PROGRAMMABLE DECODING OF A PLURALITY OF C...
- Publication number 20090309770
- Publication date Dec 17, 2009
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Decision Tree Representation of a Function
- Publication number 20090281969
- Publication date Nov 12, 2009
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20090187873
- Publication date Jul 23, 2009
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMAND LANGUAGE FOR MEMORY TESTING
- Publication number 20090133003
- Publication date May 21, 2009
- LSI Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for outputting a sequence of commands and data de...
- Publication number 20090094571
- Publication date Apr 9, 2009
- LSI CORPORATION
- Andrey A. Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRC...
- Publication number 20080295044
- Publication date Nov 27, 2008
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINED LDPC ARITHMETIC UNIT
- Publication number 20080178057
- Publication date Jul 24, 2008
- LSI Logic Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY MAPPING FOR PARALLEL TURBO DECODING
- Publication number 20080049719
- Publication date Feb 28, 2008
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data Shredding RAID Mode
- Publication number 20080046764
- Publication date Feb 21, 2008
- LSI Logic Corporation
- Mikhail I. Grinchuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for outputting a sequence of commands and data de...
- Publication number 20070169009
- Publication date Jul 19, 2007
- Andrey A. Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory timing model with back-annotating
- Publication number 20070143648
- Publication date Jun 21, 2007
- LSI Logic Corporation
- Alexander Andreev
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for generating memory models and timing database
- Publication number 20070136704
- Publication date Jun 14, 2007
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for tiling memories in integrated circuit layout
- Publication number 20070108961
- Publication date May 17, 2007
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for mapping design memories to integrated circ...
- Publication number 20070113212
- Publication date May 17, 2007
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High performance tiling for RRAM memory
- Publication number 20070091105
- Publication date Apr 26, 2007
- Alexander Andreev
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for analyzing the quality of an OPC mask
- Publication number 20070079277
- Publication date Apr 5, 2007
- Ilya Golubtsov
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Multimode delay analyzer
- Publication number 20070044053
- Publication date Feb 22, 2007
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Decomposer for parallel turbo decoding, process and integrated circuit
- Publication number 20060236194
- Publication date Oct 19, 2006
- LSI Logic Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Verification of RRAM tiling netlist
- Publication number 20060117281
- Publication date Jun 1, 2006
- Andrey A. Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RRAM memory timing learning tool
- Publication number 20060117284
- Publication date Jun 1, 2006
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory generation and placement
- Publication number 20060107247
- Publication date May 18, 2006
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING

Ranko Scepanovic

Person

Patents Grantslast 30 patents

Architectural floorplan for a structured ASIC manufactured on a 28...

Via-configurable high-performance logic block involving transistor...

Data shredding RAID mode

Via-configurable high-performance logic block architecture

Method and apparatus for generating memory models and timing database

Method and computer program for generating grounded shielding wires...

Method and apparatus for generating memory models and timing database

Method and apparatus for balancing signal delay skew

Memory mapping for parallel turbo decoding

Method and apparatus for mapping design memories to integrated circ...

Methods and apparatus for programmable decoding of a plurality of c...

Method and system for outputting a sequence of commands and data de...

Signal delay skew reduction system

Decision tree representation of a function

Command language for memory testing

Generation of test sequences during memory built-in self testing of...

High performance tiling for RRAM memory

Pipelined LDPC arithmetic unit

Method and apparatus for generating memory models and timing database

Multimode delay analysis for simplifying integrated circuit design...

Method and system for outputting a sequence of commands and data de...

Method and apparatus for mapping design memories to integrated circ...

Memory timing model with back-annotating

Method and system for outputting a sequence of commands and data de...

Method and apparatus for tiling memories in integrated circuit layout

Method and system for analyzing the quality of an OPC mask

Verification of RRAM tiling netlist

Memory mapping for parallel turbo decoding

System and method for efficiently testing a large random access mem...

Search engine for large-width data

Patents Applicationslast 30 patents

STRUCTURED INTEGRATED CIRCUIT DEVICE WITH MULTIPLE CONFIGURABLE VIA...

Architectural Floorplan for a Structured ASIC Manufactured on a 28...

Via-Configurable High-Performance Logic Block Involving Transistor...

Method and Apparatus for Generating Memory Models and Timing Database

SIGNAL DELAY SKEW REDUCTION SYSTEM

Via-Configurable High-Performance Logic Block Architecture

SIGNAL DELAY SKEW REDUCTION SYSTEM

Method and Apparatus for Generating Memory Models and Timing Database

Generation Of Test Sequences During Memory Built-In Self Testing Of...

METHODS AND APPARATUS FOR PROGRAMMABLE DECODING OF A PLURALITY OF C...

Decision Tree Representation of a Function

SIGNAL DELAY SKEW REDUCTION SYSTEM

COMMAND LANGUAGE FOR MEMORY TESTING

Method and system for outputting a sequence of commands and data de...

METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRC...

PIPELINED LDPC ARITHMETIC UNIT

MEMORY MAPPING FOR PARALLEL TURBO DECODING

Data Shredding RAID Mode

Method and system for outputting a sequence of commands and data de...

Memory timing model with back-annotating

Method and apparatus for generating memory models and timing database

Method and apparatus for tiling memories in integrated circuit layout

Method and apparatus for mapping design memories to integrated circ...

High performance tiling for RRAM memory

Method and system for analyzing the quality of an OPC mask

Multimode delay analyzer

Decomposer for parallel turbo decoding, process and integrated circuit

Verification of RRAM tiling netlist

RRAM memory timing learning tool

Memory generation and placement