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Rasoju Veerabadra Chary
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Bangalore, IN
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Patents Grants
last 30 patents
Information
Patent Grant
Bit line write assist for static random access memory architectures
Patent number
9,177,633
Issue date
Nov 3, 2015
Avago Technologies General IP (Singapore) Pte. Ltd.
Rajiv Kumar Roy
G11 - INFORMATION STORAGE
Information
Patent Grant
Dual rail single-ended read data paths for static random access mem...
Patent number
9,177,635
Issue date
Nov 3, 2015
Avago Technologies General IP (Singapore) Pte. Ltd.
Donald Albert Evans
G11 - INFORMATION STORAGE
Information
Patent Grant
Differential latch word line assist for SRAM
Patent number
9,111,637
Issue date
Aug 18, 2015
Avago Technologies General IP Singapore) Pte Ltd
Rahul Sahu
G11 - INFORMATION STORAGE
Information
Patent Grant
Address decoding circuits for reducing address and memory enable se...
Patent number
8,923,090
Issue date
Dec 30, 2014
LSI Corporation
Donald A. Evans
G11 - INFORMATION STORAGE
Information
Patent Grant
Adjusting access times to memory cells based on characterized word-...
Patent number
8,787,099
Issue date
Jul 22, 2014
LSI Corporation
Donald Albert Evans
G11 - INFORMATION STORAGE
Information
Patent Grant
Adjusting bit-line discharge time in memory arrays based on charact...
Patent number
8,773,927
Issue date
Jul 8, 2014
LSI Corporation
Donald Albert Evans
G11 - INFORMATION STORAGE
Information
Patent Grant
Dual rail power supply scheme for memories
Patent number
8,724,421
Issue date
May 13, 2014
LSI Corporation
Donald A. Evans
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Memory device with area efficient power gating circuitry
Patent number
8,462,562
Issue date
Jun 11, 2013
LSI Corporation
Ankur Goel
G11 - INFORMATION STORAGE
Patents Applications
last 30 patents
Information
Patent Application
WORD LINE DECODERS FOR DUAL RAIL STATIC RANDOM ACCESS MEMORIES
Publication number
20150302918
Publication date
Oct 22, 2015
LSI Corporation
Rajiv Kumar Roy
G11 - INFORMATION STORAGE
Information
Patent Application
BIT LINE WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARCHITECTURES
Publication number
20150255148
Publication date
Sep 10, 2015
LSI Corporation
Rajiv Kumar Roy
G11 - INFORMATION STORAGE
Information
Patent Application
MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES
Publication number
20150138864
Publication date
May 21, 2015
LSI Corporation
Donald Albert Evans
G11 - INFORMATION STORAGE
Information
Patent Application
INTERLEAVED WRITE ASSIST FOR HIERARCHICAL BITLINE SRAM ARCHITECTURES
Publication number
20150138863
Publication date
May 21, 2015
LSI Corporation
Rajiv Kumar Roy
G11 - INFORMATION STORAGE
Information
Patent Application
GLOBAL BITLINE WRITE ASSIST FOR SRAM ARCHITECTURES
Publication number
20150138876
Publication date
May 21, 2015
LSI Corporation
Rajiv Kumar Roy
G11 - INFORMATION STORAGE
Information
Patent Application
ADJUSTING BIT-LINE DISCHARGE TIME IN MEMORY ARRAYS BASED ON CHARACT...
Publication number
20140071775
Publication date
Mar 13, 2014
LSI Corporation
Donald Albert Evans
G11 - INFORMATION STORAGE
Information
Patent Application
DUAL RAIL POWER SUPPLY SCHEME FOR MEMORIES
Publication number
20140025981
Publication date
Jan 23, 2014
LSI Corporation
Donald A. Evans
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
ADJUSTING ACCESS TIMES TO MEMORY CELLS BASED ON CHARACTERIZED WORD-...
Publication number
20130343139
Publication date
Dec 26, 2013
LSI Corporation
Donald Albert Evans
G11 - INFORMATION STORAGE
Information
Patent Application
MEMORY DEVICE WITH AREA EFFICIENT POWER GATING CIRCUITRY
Publication number
20130128676
Publication date
May 23, 2013
LSI Corporation
Ankur Goel
G11 - INFORMATION STORAGE