Ravi Prakash Srivastava

Person

Beacon, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple patterning with mandrel cuts defined by block masks
- Patent number 11,417,525
- Issue date Aug 16, 2022
- GLOBALFOUNDRIES U.S. INC.
- Martin O'Toole
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal on metal multiple patterning
- Patent number 11,398,378
- Issue date Jul 26, 2022
- GLOBALFOUNDRIES Inc.
- Hsueh-Chung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method to improve overlay performance in semiconducto...
- Patent number 10,833,022
- Issue date Nov 10, 2020
- GLOBALFOUNDRIES Inc.
- Cung D. Tran
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Metal on metal multiple patterning
- Patent number 10,818,494
- Issue date Oct 27, 2020
- GLOBALFOUNDRIES Inc.
- Hsueh-Chung Chen
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Integrated circuit structure to reduce soft-fail incidence and meth...
- Patent number 10,818,557
- Issue date Oct 27, 2020
- GLOBALFOUNDRIES Inc.
- Sipeng Gu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple patterning with lithographically-defined cuts
- Patent number 10,784,119
- Issue date Sep 22, 2020
- GLOBALFOUNDRIES Inc.
- Ravi Prakash Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chamferless interconnect vias of semiconductor devices
- Patent number 10,770,344
- Issue date Sep 8, 2020
- GLOBALFOUNDRIES Inc.
- Yuping Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming smooth sidewall structures using spacer materials
- Patent number 10,714,380
- Issue date Jul 14, 2020
- GLOBALFOUNDRIES Inc.
- Ravi P. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnects with variable space mandrel cuts formed by block patt...
- Patent number 10,692,812
- Issue date Jun 23, 2020
- GLOBALFOUNDRIES Inc.
- Ravi Prakash Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lithographic patterning to form fine pitch features
- Patent number 10,504,774
- Issue date Dec 10, 2019
- GLOBALFOUNDRIES Inc.
- Sunil K. Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method to improve overlay performance in semiconducto...
- Patent number 10,504,851
- Issue date Dec 10, 2019
- GLOBALFOUNDRIES Inc.
- Cung D. Tran
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Dual photoresist approach to lithographic patterning for pitch redu...
- Patent number 10,497,610
- Issue date Dec 3, 2019
- GLOBALFOUNDRIES Inc.
- Ravi Srivastava
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
SADP method with mandrel undercut spacer portion for mandrel space...
- Patent number 10,395,941
- Issue date Aug 27, 2019
- GLOBALFOUNDRIES Inc.
- Ravi P. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect formation process using wire trench etch prior to via...
- Patent number 10,347,528
- Issue date Jul 9, 2019
- GLOBALFOUNDRIES Inc.
- Sunil K. Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structure with method of forming the same
- Patent number 10,312,188
- Issue date Jun 4, 2019
- GLOBALFOUNDRIES Inc.
- Ravi P. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned multiple patterning processes using bi-layer mandrels...
- Patent number 10,192,780
- Issue date Jan 29, 2019
- GLOBALFOUNDRIES Inc.
- Xiaohan Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and devices for back end of line via formation
- Patent number 9,691,654
- Issue date Jun 27, 2017
- GLOBALFOUNDRIES Inc.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and devices for metal filling processes
- Patent number 9,613,909
- Issue date Apr 4, 2017
- GLOBALFOUNDRIES Inc.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits including organic interlayer dielectric layers...
- Patent number 9,576,894
- Issue date Feb 21, 2017
- GLOBALFOUNDRIES, INC.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of fabricating BEOL interlayer structures
- Patent number 9,362,162
- Issue date Jun 7, 2016
- GLOBALFOUNDRIES Inc.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and structures for back end of line integration
- Patent number 9,293,363
- Issue date Mar 22, 2016
- GLOBALFOUNDRIES Inc.
- Sunil K. Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and structures for back end of line integration
- Patent number 9,117,822
- Issue date Aug 25, 2015
- GLOBALFOUNDRIES Inc.
- Sunil K. Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Critical dimension and pattern recognition structures for devices m...
- Patent number 8,932,961
- Issue date Jan 13, 2015
- GLOBALFOUNDRIES Inc.
- Sohan Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to reduce depth delta between dense and wide features in dua...
- Patent number 8,822,342
- Issue date Sep 2, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Ravi Prakash Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system with ultra-low k dielectric and method of...
- Patent number 8,420,947
- Issue date Apr 16, 2013
- Globalfoudries Singapore Pte. Ltd.
- Ravi Prakash Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a conductive interconnect arrangement for a s...
- Patent number 8,183,149
- Issue date May 22, 2012
- GLOBALFOUNDRIES Inc.
- David M. Permana
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and structures to enable self-aligned via etch for Cu damas...
- Patent number 8,114,769
- Issue date Feb 14, 2012
- Globalfoundries Singapore Pte, Lte.
- Ravi Prakash Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of patterning insulating layers using etching techniques th...
- Patent number 8,058,176
- Issue date Nov 15, 2011
- Samsung Electronics Co., Ltd.
- Wan-jae Park
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
STRUCTURE WITH BARRIER-FREE METAL VIA AND METAL WIRE INCLUDING NON-...
- Publication number 20250191805
- Publication date Jun 12, 2025
- GLOBALFOUNDRIES U.S. Inc.
- Ravi Prakash Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID BONDING WITH SELECTIVELY FORMED DIELECTRIC MATERIAL
- Publication number 20250149499
- Publication date May 8, 2025
- GLOBALFOUNDRIES U.S. Inc.
- Ravi Prakash SRIVASTAVA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-SUBSTRATE COUPLING FOR PHOTONIC INTEGRATED CIRCUITS
- Publication number 20240427095
- Publication date Dec 26, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Ravi Prakash Srivastava
- G02 - OPTICS
Information Patent Application
OPTICAL PHASE SHIFTER WITH ONE OR MORE INTEGRATED THERMOELECTRIC DE...
- Publication number 20240231173
- Publication date Jul 11, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Vibhor Jain
- F25 - REFRIGERATION OR COOLING COMBINED HEATING AND REFRIGERATION SYSTEMS HEA...
Information Patent Application
WAVEGUIDE CORES SURROUNDED BY AN AIRGAP
- Publication number 20240192442
- Publication date Jun 13, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Ravi Prakash Srivastava
- G02 - OPTICS
Information Patent Application
ENLARGED MULTILAYER NITRIDE WAVEGUIDE FOR PHOTONIC INTEGRATED CIRCUIT
- Publication number 20240176067
- Publication date May 30, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Shesh Mani Pandey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE WITH INDUCTOR EMBEDDED IN BONDED SEMICONDUCTOR SUBSTRATES...
- Publication number 20240145382
- Publication date May 2, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Ravi P. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL ON METAL MULTIPLE PATTERNING
- Publication number 20210005454
- Publication date Jan 7, 2021
- GLOBALFOUNDRIES INC.
- Hsueh-Chung CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHAMFERLESS INTERCONNECT VIAS OF SEMICONDUCTOR DEVICES
- Publication number 20200219763
- Publication date Jul 9, 2020
- GLOBALFOUNDRIES INC.
- YUPING REN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SMOOTH SIDEWALL STRUCTURES
- Publication number 20200135545
- Publication date Apr 30, 2020
- GLOBALFOUNDRIES INC.
- Ravi P. SRIVASTAVA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE PATTERNING WITH MANDREL CUTS DEFINED BY BLOCK MASKS
- Publication number 20200111668
- Publication date Apr 9, 2020
- GLOBALFOUNDRIES INC.
- Martin O'Toole
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE PATTERNING WITH LITHOGRAPHICALLY-DEFINED CUTS
- Publication number 20200111677
- Publication date Apr 9, 2020
- GLOBALFOUNDRIES INC.
- Ravi Prakash Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL ON METAL MULTIPLE PATTERNING
- Publication number 20200083043
- Publication date Mar 12, 2020
- GLOBALFOUNDRIES INC.
- Hsueh-Chung CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD TO IMPROVE OVERLAY PERFORMANCE IN SEMICONDUCTO...
- Publication number 20200051923
- Publication date Feb 13, 2020
- GLOBALFOUNDRIES INC.
- Cung D. Tran
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE TO REDUCE SOFT-FAIL INCIDENCE AND METH...
- Publication number 20200013678
- Publication date Jan 9, 2020
- GLOBALFOUNDRIES INC.
- Sipeng Gu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECTS WITH VARIABLE SPACE MANDREL CUTS FORMED BY BLOCK PATT...
- Publication number 20190355658
- Publication date Nov 21, 2019
- GLOBALFOUNDRIES INC.
- Ravi Prakash Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD TO IMPROVE OVERLAY PERFORMANCE IN SEMICONDUCTO...
- Publication number 20190267329
- Publication date Aug 29, 2019
- GLOBALFOUNDRIES INC.
- Cung D. Tran
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
AIR GAP FORMATION IN BACK-END-OF-LINE STRUCTURES
- Publication number 20190237356
- Publication date Aug 1, 2019
- GLOBALFOUNDRIES INC.
- Ravi Prakash Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL DEVELOPING METHODS FOR LITHOGRAPHY PATTERNING
- Publication number 20190079408
- Publication date Mar 14, 2019
- GLOBALFOUNDRIES INC.
- Sohan Singh Mehta
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
DUAL PHOTORESIST APPROACH TO LITHOGRAPHIC PATTERNING FOR PITCH REDU...
- Publication number 20180158723
- Publication date Jun 7, 2018
- GLOBALFOUNDRIES INC.
- Ravi Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LITHOGRAPHIC PATTERNING TO FORM FINE PITCH FEATURES
- Publication number 20180025936
- Publication date Jan 25, 2018
- GLOBALFOUNDRIES INC.
- Sunil K. Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND DEVICES FOR METAL FILLING PROCESSES
- Publication number 20170186688
- Publication date Jun 29, 2017
- GLOBALFOUNDRIES INC.
- Sunil Kumar SINGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND DEVICES FOR BACK END OF LINE VIA FORMATION
- Publication number 20170178953
- Publication date Jun 22, 2017
- GLOBALFOUNDRIES INC.
- Sunil Kumar SINGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND DEVICES FOR METAL FILLING PROCESSES
- Publication number 20170047290
- Publication date Feb 16, 2017
- GLOBALFOUNDRIES INC.
- Sunil Kumar SINGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION
- Publication number 20170025347
- Publication date Jan 26, 2017
- GLOBALFOUNDRIES INC.
- Sunil K. Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS INCLUDING ORGANIC INTERLAYER DIELECTRIC LAYERS...
- Publication number 20160358851
- Publication date Dec 8, 2016
- GLOBALFOUNDRIES, Inc.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FABRICATING BEOL INTERLAYER STRUCTURES
- Publication number 20160049327
- Publication date Feb 18, 2016
- GLOBALFOUNDRIES INC.
- Sunil Kumar SINGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION
- Publication number 20150332959
- Publication date Nov 19, 2015
- GLOBALFOUNDRIES INC.
- Sunil K. Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CRITICAL DIMENSION AND PATTERN RECOGNITION STRUCTURES FOR DEVICES M...
- Publication number 20150050811
- Publication date Feb 19, 2015
- GLOBALFOUNDRIES INC.
- Sohan Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Critical Dimension and Pattern Recognition Structures for Devices M...
- Publication number 20130207108
- Publication date Aug 15, 2013
- GLOBALFOUNDRIES INC.
- Sohan Mehta
- H01 - BASIC ELECTRIC ELEMENTS

Ravi Prakash Srivastava

Person

Patents Grantslast 30 patents

Multiple patterning with mandrel cuts defined by block masks

Metal on metal multiple patterning

Structure and method to improve overlay performance in semiconducto...

Metal on metal multiple patterning

Integrated circuit structure to reduce soft-fail incidence and meth...

Multiple patterning with lithographically-defined cuts

Chamferless interconnect vias of semiconductor devices

Method of forming smooth sidewall structures using spacer materials

Interconnects with variable space mandrel cuts formed by block patt...

Lithographic patterning to form fine pitch features

Structure and method to improve overlay performance in semiconducto...

Dual photoresist approach to lithographic patterning for pitch redu...

SADP method with mandrel undercut spacer portion for mandrel space...

Interconnect formation process using wire trench etch prior to via...

Interconnect structure with method of forming the same

Self-aligned multiple patterning processes using bi-layer mandrels...

Methods and devices for back end of line via formation

Methods and devices for metal filling processes

Integrated circuits including organic interlayer dielectric layers...

Methods of fabricating BEOL interlayer structures

Methods and structures for back end of line integration

Methods and structures for back end of line integration

Critical dimension and pattern recognition structures for devices m...

Method to reduce depth delta between dense and wide features in dua...

Integrated circuit system with ultra-low k dielectric and method of...

Method of fabricating a conductive interconnect arrangement for a s...

Methods and structures to enable self-aligned via etch for Cu damas...

Methods of patterning insulating layers using etching techniques th...

Patents Applicationslast 30 patents

STRUCTURE WITH BARRIER-FREE METAL VIA AND METAL WIRE INCLUDING NON-...

HYBRID BONDING WITH SELECTIVELY FORMED DIELECTRIC MATERIAL

MULTI-SUBSTRATE COUPLING FOR PHOTONIC INTEGRATED CIRCUITS

OPTICAL PHASE SHIFTER WITH ONE OR MORE INTEGRATED THERMOELECTRIC DE...

WAVEGUIDE CORES SURROUNDED BY AN AIRGAP

ENLARGED MULTILAYER NITRIDE WAVEGUIDE FOR PHOTONIC INTEGRATED CIRCUIT

STRUCTURE WITH INDUCTOR EMBEDDED IN BONDED SEMICONDUCTOR SUBSTRATES...

METAL ON METAL MULTIPLE PATTERNING

CHAMFERLESS INTERCONNECT VIAS OF SEMICONDUCTOR DEVICES

SMOOTH SIDEWALL STRUCTURES

MULTIPLE PATTERNING WITH MANDREL CUTS DEFINED BY BLOCK MASKS

MULTIPLE PATTERNING WITH LITHOGRAPHICALLY-DEFINED CUTS

METAL ON METAL MULTIPLE PATTERNING

STRUCTURE AND METHOD TO IMPROVE OVERLAY PERFORMANCE IN SEMICONDUCTO...

INTEGRATED CIRCUIT STRUCTURE TO REDUCE SOFT-FAIL INCIDENCE AND METH...

INTERCONNECTS WITH VARIABLE SPACE MANDREL CUTS FORMED BY BLOCK PATT...

STRUCTURE AND METHOD TO IMPROVE OVERLAY PERFORMANCE IN SEMICONDUCTO...

AIR GAP FORMATION IN BACK-END-OF-LINE STRUCTURES

DUAL DEVELOPING METHODS FOR LITHOGRAPHY PATTERNING

DUAL PHOTORESIST APPROACH TO LITHOGRAPHIC PATTERNING FOR PITCH REDU...

LITHOGRAPHIC PATTERNING TO FORM FINE PITCH FEATURES

METHODS AND DEVICES FOR METAL FILLING PROCESSES

METHODS AND DEVICES FOR BACK END OF LINE VIA FORMATION

METHODS AND DEVICES FOR METAL FILLING PROCESSES

METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION

INTEGRATED CIRCUITS INCLUDING ORGANIC INTERLAYER DIELECTRIC LAYERS...

METHODS OF FABRICATING BEOL INTERLAYER STRUCTURES

METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION

CRITICAL DIMENSION AND PATTERN RECOGNITION STRUCTURES FOR DEVICES M...

Critical Dimension and Pattern Recognition Structures for Devices M...