RAVINDRANATH V. MAHAJAN

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Embedded bridge die with through-silicon vias
- Patent number 12,159,813
- Issue date Dec 3, 2024
- Intel Corporation
- Aditya S. Vaidya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Active bridge enabled co-packaged photonic transceiver
- Patent number 12,148,742
- Issue date Nov 19, 2024
- Intel Corporation
- Thomas Liljeberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die ultrafine pitch patch architecture of interconnect bridge...
- Patent number 12,142,568
- Issue date Nov 12, 2024
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nested architectures for enhanced heterogeneous integration
- Patent number 12,142,545
- Issue date Nov 12, 2024
- Intel Corporation
- Ravindranath Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structural elements for application specific electronic device pack...
- Patent number 12,074,102
- Issue date Aug 27, 2024
- Intel Corporation
- Suddhasattwa Nad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patch on interposer architecture for low cost optical co-packaging
- Patent number 12,061,371
- Issue date Aug 13, 2024
- Intel Corporation
- Xiaoqian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heat dissipation device having shielding/containment extensions
- Patent number 12,048,123
- Issue date Jul 23, 2024
- Intel Corporation
- Aastha Uppal
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Interconnect architecture with silicon interposer and EMIB
- Patent number 11,901,299
- Issue date Feb 13, 2024
- Intel Corporation
- Md Altaf Hossain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Distributed semiconductor die and package architecture
- Patent number 11,894,359
- Issue date Feb 6, 2024
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Full package vapor chamber with IHS
- Patent number 11,832,419
- Issue date Nov 28, 2023
- Intel Corporation
- Nicholas Neal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-sided co-packaged optics for high bandwidth networking applica...
- Patent number 11,830,863
- Issue date Nov 28, 2023
- Intel Corporation
- Suresh V. Pothukuchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heterogeneous nested interposer package for IC chips
- Patent number 11,824,018
- Issue date Nov 21, 2023
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct liquid micro jet (DLMJ) structures for addressing thermal pe...
- Patent number 11,804,418
- Issue date Oct 31, 2023
- Intel Corporation
- Nicholas Neal
- F28 - HEAT EXCHANGE IN GENERAL
Information Patent Grant
Nested architectures for enhanced heterogeneous integration
- Patent number 11,798,865
- Issue date Oct 24, 2023
- Intel Corporation
- Ravindranath Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultrathin bridge and multi-die ultrafine pitch patch architecture a...
- Patent number 11,756,889
- Issue date Sep 12, 2023
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package architecture including thermoelectric cooler structures
- Patent number 11,756,856
- Issue date Sep 12, 2023
- Intel Corporation
- Krishna Vasanth Valavala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC package including multi-chip unit with bonded integrated heat sp...
- Patent number 11,749,577
- Issue date Sep 5, 2023
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple die package using an embedded bridge connecting dies
- Patent number 11,742,293
- Issue date Aug 29, 2023
- Intel Corporation
- Yidnekachew S. Mekonnen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nested architectures for enhanced heterogeneous integration
- Patent number 11,742,261
- Issue date Aug 29, 2023
- Intel Corporation
- Ravindranath Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heterogeneous nested interposer package for IC chips
- Patent number 11,735,533
- Issue date Aug 22, 2023
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked die cavity package
- Patent number 11,705,377
- Issue date Jul 18, 2023
- Intel Corporation
- Mitul Modi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die ultrafine pitch patch architecture and method of making
- Patent number 11,694,959
- Issue date Jul 4, 2023
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solid state thermoelectric cooler in silicon backend layers for fas...
- Patent number 11,664,293
- Issue date May 30, 2023
- Intel Corporation
- Krishna Vasanth Valavala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable logic device with fine-grained disaggregation
- Patent number 11,595,045
- Issue date Feb 28, 2023
- Intel Corporation
- Dheeraj Subbareddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded bridge with through-silicon vias
- Patent number 11,587,851
- Issue date Feb 21, 2023
- Intel Corporation
- Aditya S. Vaidya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC package including multi-chip unit with bonded integrated heat sp...
- Patent number 11,581,235
- Issue date Feb 14, 2023
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge hub tiling architecture
- Patent number 11,569,173
- Issue date Jan 31, 2023
- Intel Corporation
- Andrew P. Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect architecture with silicon interposer and EMIB
- Patent number 11,557,541
- Issue date Jan 17, 2023
- Intel Corporation
- Md Altaf Hossain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal management solutions for integrated circuit packages
- Patent number 11,545,407
- Issue date Jan 3, 2023
- Intel Corporation
- Kumar Abhishek Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having passive support wafer
- Patent number 11,417,630
- Issue date Aug 16, 2022
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
EMBEDDED PHOTONIC INTEGRATED CIRCUITS
- Publication number 20240329301
- Publication date Oct 3, 2024
- Intel Corporation
- Kaveh Hosseini
- G02 - OPTICS
Information Patent Application
PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...
- Publication number 20240222321
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...
- Publication number 20240222326
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...
- Publication number 20240222328
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LIQUID METAL WELLS FOR INTERCONNECT ARCHITECTURES
- Publication number 20240213156
- Publication date Jun 27, 2024
- Intel Corporation
- Kristof DARMAWIKARTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN FILM CAPACITORS (TFCS) IN ETCHED BACK DEEP VIA
- Publication number 20240213132
- Publication date Jun 27, 2024
- Intel Corporation
- Kristof DARMAWIKARTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGES INCLUDING SUBSTRATES WITH STRENGTHENED...
- Publication number 20240178146
- Publication date May 30, 2024
- Intel Corporation
- Benjamin T. Duong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH MICROFLUIDIC CHANNELS IN GLASS SUBSTRATES
- Publication number 20240162158
- Publication date May 16, 2024
- Intel Corporation
- Brandon C. Marin
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
INTERCONNECT ARCHITECTURE WITH SILICON INTERPOSER AND EMIB
- Publication number 20240145395
- Publication date May 2, 2024
- Intel Corporation
- MD Altaf HOSSAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
- Publication number 20240128162
- Publication date Apr 18, 2024
- Intel Corporation
- Ravindranath MAHAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS
- Publication number 20240128205
- Publication date Apr 18, 2024
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL SIDED EMBEDDED PASSIVES VIA PANEL LEVEL THERMAL COMPRESSION BO...
- Publication number 20240113000
- Publication date Apr 4, 2024
- Intel Corporation
- Kristof Darmawikarta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE PERMANENT GLASS ARCHITECTURES FOR STACKED INTEGRAT...
- Publication number 20240113087
- Publication date Apr 4, 2024
- Intel Corporation
- Brandon Marin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH MIXED COPPER AND SOLDER INTERCONNEC...
- Publication number 20240096809
- Publication date Mar 21, 2024
- Intel Corporation
- Hiroki Tanaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GLASS DIE-TO-DIE BRIDGE AND INTERPOSER FOR DIE FIRST ARCHITECTURE
- Publication number 20240071935
- Publication date Feb 29, 2024
- Intel Corporation
- Brandon C. MARIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES WITH GLASS CORES FOR THICKNESS REDUCTION AND...
- Publication number 20240063203
- Publication date Feb 22, 2024
- Intel Corporation
- Brandon C. MARIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANGLED BAFFLES ON GLASS EDGE FOR CAVITATION PROTECTION
- Publication number 20240063069
- Publication date Feb 22, 2024
- Intel Corporation
- Brandon C. MARIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS
- Publication number 20240038687
- Publication date Feb 1, 2024
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES INCLUDING STACKED DIES COUPLED BY A THRO...
- Publication number 20240006366
- Publication date Jan 4, 2024
- Intel Corporation
- Stephen Morein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES INCLUDING STACKED DIES COUPLED BY A THRO...
- Publication number 20240006381
- Publication date Jan 4, 2024
- Intel Corporation
- Stephen Morein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE OF SCALABLE COMPUTE WALL HAVING COMPUTE BRICK...
- Publication number 20240006395
- Publication date Jan 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID BONDING WITH PHOTONIC INTEGRATED CIRCUITS FOR HIGH BANDWIDTH...
- Publication number 20240004129
- Publication date Jan 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH COMPUTE BRICKS HAVING VERTICALLY STACKED...
- Publication number 20240006375
- Publication date Jan 4, 2024
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH IN...
- Publication number 20230420411
- Publication date Dec 28, 2023
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE OF PHOTONIC SYSTEM WITH VERTICALLY STACKED DIE...
- Publication number 20230420432
- Publication date Dec 28, 2023
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT D...
- Publication number 20230420436
- Publication date Dec 28, 2023
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT D...
- Publication number 20230420409
- Publication date Dec 28, 2023
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH VERTICALLY STACKED BRIDGE DIES HAVING PLA...
- Publication number 20230420410
- Publication date Dec 28, 2023
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
- Publication number 20230411245
- Publication date Dec 21, 2023
- Intel Corporation
- Ravindranath MAHAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SP...
- Publication number 20230360994
- Publication date Nov 9, 2023
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS

RAVINDRANATH V. MAHAJAN

Person

Patents Grantslast 30 patents

Embedded bridge die with through-silicon vias

Active bridge enabled co-packaged photonic transceiver

Multi-die ultrafine pitch patch architecture of interconnect bridge...

Nested architectures for enhanced heterogeneous integration

Structural elements for application specific electronic device pack...

Patch on interposer architecture for low cost optical co-packaging

Heat dissipation device having shielding/containment extensions

Interconnect architecture with silicon interposer and EMIB

Distributed semiconductor die and package architecture

Full package vapor chamber with IHS

Dual-sided co-packaged optics for high bandwidth networking applica...

Heterogeneous nested interposer package for IC chips

Direct liquid micro jet (DLMJ) structures for addressing thermal pe...

Nested architectures for enhanced heterogeneous integration

Ultrathin bridge and multi-die ultrafine pitch patch architecture a...

Package architecture including thermoelectric cooler structures

IC package including multi-chip unit with bonded integrated heat sp...

Multiple die package using an embedded bridge connecting dies

Nested architectures for enhanced heterogeneous integration

Heterogeneous nested interposer package for IC chips

Stacked die cavity package

Multi-die ultrafine pitch patch architecture and method of making

Solid state thermoelectric cooler in silicon backend layers for fas...

Programmable logic device with fine-grained disaggregation

Embedded bridge with through-silicon vias

IC package including multi-chip unit with bonded integrated heat sp...

Bridge hub tiling architecture

Interconnect architecture with silicon interposer and EMIB

Thermal management solutions for integrated circuit packages

Semiconductor package having passive support wafer

Patents Applicationslast 30 patents

EMBEDDED PHOTONIC INTEGRATED CIRCUITS

PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...

PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...

PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...

LIQUID METAL WELLS FOR INTERCONNECT ARCHITECTURES

THIN FILM CAPACITORS (TFCS) IN ETCHED BACK DEEP VIA

INTEGRATED CIRCUIT PACKAGES INCLUDING SUBSTRATES WITH STRENGTHENED...

PACKAGE ARCHITECTURE WITH MICROFLUIDIC CHANNELS IN GLASS SUBSTRATES

INTERCONNECT ARCHITECTURE WITH SILICON INTERPOSER AND EMIB

NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION

HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS

DUAL SIDED EMBEDDED PASSIVES VIA PANEL LEVEL THERMAL COMPRESSION BO...

HIGH PERFORMANCE PERMANENT GLASS ARCHITECTURES FOR STACKED INTEGRAT...

MICROELECTRONIC ASSEMBLIES WITH MIXED COPPER AND SOLDER INTERCONNEC...

GLASS DIE-TO-DIE BRIDGE AND INTERPOSER FOR DIE FIRST ARCHITECTURE

PACKAGE ARCHITECTURES WITH GLASS CORES FOR THICKNESS REDUCTION AND...

ANGLED BAFFLES ON GLASS EDGE FOR CAVITATION PROTECTION

HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS

MICROELECTRONIC ASSEMBLIES INCLUDING STACKED DIES COUPLED BY A THRO...

MICROELECTRONIC ASSEMBLIES INCLUDING STACKED DIES COUPLED BY A THRO...

PACKAGE ARCHITECTURE OF SCALABLE COMPUTE WALL HAVING COMPUTE BRICK...

HYBRID BONDING WITH PHOTONIC INTEGRATED CIRCUITS FOR HIGH BANDWIDTH...

PACKAGE ARCHITECTURE WITH COMPUTE BRICKS HAVING VERTICALLY STACKED...

PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH IN...

PACKAGE ARCHITECTURE OF PHOTONIC SYSTEM WITH VERTICALLY STACKED DIE...

PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT D...

PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT D...

PACKAGE ARCHITECTURE WITH VERTICALLY STACKED BRIDGE DIES HAVING PLA...

NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION

IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SP...