Patent Application
20240096809
Integrated circuit (IC) devices (e.g., dies) are typically coupled together in a multi-die IC package to integrate features or functionality and to facilitate connections to other components, such as package substrates. IC packages may include a bridge component or an embedded multi-die interconnect bridge (EMIB) for coupling two or more IC dies.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings.
Microelectronic assemblies, related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate having a surface including first conductive contacts and second conductive contacts, wherein the first conductive contacts have a first thickness and the second conductive contacts have a second thickness different than the first thickness; a first microelectronic component having third conductive contacts, wherein respective ones of the third conductive contacts are coupled to respective ones of the first conductive contacts by first interconnects, wherein the first interconnects include solder having a thickness between 2 microns and 35 microns; and a second microelectronic component having fourth conductive contact, wherein respective ones of the fourth conductive contacts are coupled to respective ones of the second conductive contacts by second interconnects, wherein the second interconnects include solder having a thickness between 5 microns and 50 microns.
As demands for high performance computing (HPC) continue to rise, heterogeneous integration (HI) has become an important performance enabler in the microelectronics industry by providing the flexibility of die disaggregation and the ability to mix and match different intellectual property (IP) blocks on different silicon nodes in a single IC package, as referred to herein as multi-die IC packages. A focus of HI scaling is to optimize interconnect density with increased bandwidth and improved power efficiency. Conventional 2.5-dimensional (2.5D) and 3-dimensional (3D) advanced packaging architectures increase planar and 3D input/output (I/O) wire/area density for higher bandwidth requirements, and enable more effective HI-based die disaggregation. Multi-die IC packages require a significant level of design for placing heterogeneous die and mixing of components to optimize system and product performance. For example, multi-die IC packages that include different silicon technology nodes and large form factor die stitching capability with a high number of bridges embedded in the package substrate require a high level of design to integrate the components together. Multi-die IC packages may also include multiple stacked die subassemblies, which enables greater computing performance, but further increases design complexity. In emerging multi-die IC packaging architectures, interconnect bump pitch between different components must be further reduced, which increases design and manufacturing complexity due to stringent on package requirements of total thickness variation (TTV) and bump thickness variation (BTV). Various ones of the embodiments disclosed herein may help reduce the cost and complexity associated with assembling multi-die IC packages relative to conventional approaches by incorporating conductive contacts with different thickness that form interconnects having different solder thicknesses to meet TTV and BTV manufacturing requirements. Further, the embodiments disclosed herein may enable flexible designs for extremely complex heterogeneous packages for future high performance computing needs, which may in result in reduced development timelines and decreased time to market.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. The accompanying drawings are not necessarily drawn to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features. It is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using, e.g., images of suitable characterization tools such as scanning electron microscopy (SEM) images, transmission electron microscope (TEM) images, or non-contact profilometer. In such images of real structures, possible processing and/or surface defects could also be visible, e.g., surface roughness, curvature or profile deviation, pit or scratches, not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region(s), and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication and/or packaging.
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a “package” and an “IC package” are synonymous, as are a “die” and an “IC die.” The terms “top” and “bottom” may be used herein to explain various features of the drawings, but these terms are simply for ease of discussion, and do not imply a desired or required orientation. As used herein, the term “insulating” means “electrically insulating,” unless otherwise specified. Throughout the specification, and in the claims, the term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.” Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value (e.g., within +/−5 or 10% of a target value) based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art.
When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y. For convenience, the phrase “
As used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components (e.g., part of a conductive interconnect); conductive contacts may be recessed in, flush with, or extending away (e.g., having a pillar shape) from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket, or portion of a conductive line or via). In a general sense, an “interconnect” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, facilitating communication of electrical signals between them; an optical interconnect provides optical connectivity between two optical components, facilitating communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are comprised in the term “interconnect.” The nature of the interconnect being described is to be understood herein with reference to the signal medium associated therewith. Thus, when used with reference to an electronic device, such as an IC that operates using electrical signals, the term “interconnect” describes any element formed of an electrically conductive material for providing electrical connectivity to one or more elements associated with the IC or/and between various such elements. In such cases, the term “interconnect” may refer to both conductive traces (also sometimes referred to as “metal traces,” “lines,” “metal lines,” “wires,” “metal wires,” “trenches,” or “metal trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). Sometimes, electrically conductive traces and vias may be referred to as “conductive traces” and “conductive vias”, respectively, to highlight the fact that these elements include electrically conductive materials such as metals. Likewise, when used with reference to a device that operates on optical signals as well, such as a photonic IC (PIC), “interconnect” may also describe any element formed of a material that is optically conductive for providing optical connectivity to one or more elements associated with the PIC. In such cases, the term “interconnect” may refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fiber, optical splitters, optical combiners, optical couplers, and optical vias.
The substrate 107 may include a dielectric material 112 and a conductive material 108 (e.g., lines/traces/pads and vias, as shown) with the conductive material 108 arranged in the dielectric material 112 to provide conductive pathways through the substrate 107. The dielectric material 112 in the substrate 107 may be formed in layers. In some embodiments, the dielectric material 112 may include an organic material, such as an organic buildup film. In some embodiments, the dielectric material 112 may include a ceramic, an epoxy film having filler particles therein, glass, an inorganic material, or combinations of organic and inorganic materials, for example. In some embodiments, the conductive material 108 may include a metal (e.g., copper). In some embodiments, the substrate 107 may include layers of dielectric material 112/conductive material 108, with lines/traces/pads of conductive material 108 in one layer electrically coupled to lines/traces/pads of conductive material 108 in an adjacent layer by vias of the conductive material 108 extending through the dielectric material 112. A substrate 107 including such layers may be formed using a printed circuit board (PCB) fabrication technique, for example.
A substrate 107 may include N such metal layers, where N is an integer greater than or equal to one; in the accompanying drawings, the layers are labeled in descending order from the second surface 170-2 of the substrate 107 (e.g., layer N, layer N−1, layer N−2, etc.). In particular, as shown in
A substrate 107 may further include a surface insulation material 117. The surface insulation material 117 may include a solder resist and/or other dielectric materials that may provide surface electrical insulation and may be compatible with solder-based or non-solder based interconnects, as appropriate.
Although a particular number and arrangement of layers of dielectric material 112/conductive material 108 are shown in various ones of the accompanying figures, these particular numbers and arrangements are simply illustrative, and any desired number and arrangement of dielectric material 112/conductive material 108 may be used. Further, although a particular number of layers are shown in the substrate 107 (e.g., four layers), these layers may represent only a portion of the substrate 107, for example, further layers may be present (e.g., layers N−5, N−6, N−7, etc.). As shown in
The substrate 107 may further include a bridge die 114-1 surrounded by the dielectric material 112 of the substrate 107 (e.g., the bridge die 114-1 may be embedded in the dielectric material 112 of the substrate 107). The bridge die 114-1 may include a bottom surface (e.g., the surface facing towards the first surface 170-1) and an opposing top surface (e.g., the surface facing towards the second surface 170-2) with conductive contacts 124. In some embodiments, a pitch of the conductive contacts 124 on the bridge die 114-1 maybe between 5 microns and 120 microns. As used herein, pitch is measured center-to-center (e.g., from a center of a conductive contact to a center of an adjacent conductive contact). In some embodiments, as shown in
As shown in
As used herein, the terms “die,” “microelectronic component,” and similar variations may be used interchangeably. The die 114 may include other conductive pathways (e.g., including lines and vias) and/or to other circuitry (not shown) coupled to the respective conductive contacts (e.g., conductive contacts 122, 124) on the surface of the die 114. The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive pathways formed through the insulating material. In some embodiments, the insulating material of a die 114 may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, polyimide materials, glass reinforced epoxy matrix materials, or a low-k or ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymeric dielectrics, photo-imageable dielectrics, and/or benzocyclobutene-based polymers). In some embodiments, the insulating material of a die 114 may include a semiconductor material, such as silicon, germanium, or a Ill-V material (e.g., gallium nitride), and one or more additional materials. For example, an insulating material may include silicon oxide or silicon nitride. The conductive pathways in a die 114 may include conductive traces and/or conductive vias, and may connect any of the conductive contacts in the die 114 in any suitable manner (e.g., connecting multiple conductive contacts on a same surface or on different surfaces of the die 114). Example structures that may be included in the dies 114 disclosed herein are discussed below with reference to
As shown in
As shown in
In some embodiments, the die 114 may include conductive pathways to route power, ground, and/or signals to/from other dies 114 included in the microelectronic assembly 100. For example, the die 114-1 may include TSVs, including a conductive material via, such as a metal via, isolated from the surrounding silicon or other semiconductor material by a barrier oxide), or other conductive pathways through which power, ground, and/or signals may be transmitted between the package substrate 102 and one or more dies 114 “on top” of the die 114-1 (e.g., in the embodiment of
In some embodiments, the package substrate 102 may be a lower density medium and the die 114 may be a higher density medium or have an area with a higher density medium. As used herein, the term “lower density” and “higher density” are relative terms indicating that the conductive pathways (e.g., including conductive interconnects, conductive lines, and conductive vias) in a lower density medium are larger and/or have a greater pitch than the conductive pathways in a higher density medium. In some embodiments, a higher density medium may be manufactured using a modified semi-additive process or a semi-additive build-up process with advanced lithography (with small vertical interconnect features formed by advanced laser or lithography processes), while a lower density medium may be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process using etch chemistry to remove areas of unwanted copper, and with coarse vertical interconnect features formed by a standard laser process). In other embodiments, the higher density medium may be manufactured using semiconductor fabrication process, such as a single damascene process or a dual damascene process. In some embodiments, additional dies may be disposed on the top surface of the dies 114-2, 114-3. In some embodiments, additional components may be disposed on the top surface of the dies 114-2, 114-3. Additional passive components, such as surface-mount resistors, capacitors, and/or inductors, may be disposed on the top surface or the bottom surface of the package substrate 102, or embedded in the package substrate 102.
The microelectronic assembly 100 of
The STPS interconnects 150 disclosed herein may take any suitable form. In some embodiments, a set of STPS interconnects 150 may include solder (e.g., solder bumps or balls that are subject to a thermal reflow to form the STPS interconnects 150), for example, as shown in
The DTD interconnects 130 disclosed herein may take any suitable form. The DTD interconnects 130 may have a finer pitch than the STPS interconnects 150 in a microelectronic assembly. In some embodiments, the dies 114 on either side of a set of DTD interconnects 130 may be unpackaged dies, and/or the DTD interconnects 130 may include small conductive bumps (e.g., copper bumps). The DTD interconnects 130 may have too fine a pitch to couple to the package substrate 102 directly (e.g., too fine to serve as DTS interconnects 140 or STPS interconnects 150). In some embodiments, a set of DTD interconnects 130 may include solder. In some embodiments, a set of DTD interconnects 130 may include an anisotropic conductive material, such as any of the materials discussed above. In some embodiments, the DTD interconnects 130 may be used as data transfer lanes, while the STPS interconnects 150 may be used for power and ground lines, among others. In some embodiments, some of the interconnects disclosed herein in a microelectronic assembly 100 may be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or plated interconnects). In such embodiments, the interconnects may be bonded together (e.g., under elevated pressure and/or temperature) without the use of intervening solder or an anisotropic conductive material. Any of the conductive contacts disclosed herein (e.g., the conductive contacts 122, 124, 144, and/or 146) may include bond pads, solder bumps, conductive posts, or any other suitable conductive contact, for example. In some embodiments, some or all of the DTD interconnects 130 and/or the DTS interconnects 140 in a microelectronic assembly 100 may be solder interconnects that include a solder with a higher melting point than a solder included in some or all of the STPS interconnects 150. For example, when the DTD interconnects 130 and the DTS interconnects 140 in a microelectronic assembly 100 are formed before the STPS interconnects 150 are formed, solder-based DTD interconnects 130 and DTS interconnects 140 may use a higher-temperature solder (e.g., with a melting point above 200 degrees Celsius), while the STPS interconnects 150 may use a lower-temperature solder (e.g., with a melting point below 200 degrees Celsius). In some embodiments, a higher-temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, a lower-temperature solder may include tin and bismuth (e.g., eutectic tin bismuth) or tin, silver, and bismuth. In some embodiments, a lower-temperature solder may include indium, indium and tin, or gallium.
In the microelectronic assemblies 100 disclosed herein, some or all of the DTS interconnects 140 and the STPS interconnects 150 may have a larger pitch than some or all of the DTD interconnects 130. DTD interconnects 130 may have a smaller pitch than STPS interconnects 150 due to the greater similarity of materials in the different dies 114 on either side of a set of DTD interconnects 130 than between the substrate 107 and the top level dies 114-2, 114-3 on either side of a set of DTS interconnects 140, and between the substrate 107 and the package substrate 102 on either side of a set of STPS interconnects 150. In particular, the differences in the material composition of a substrate 107 and a die 114 or a package substrate 102 may result in differential expansion and contraction due to heat generated during operation (as well as the heat applied during various manufacturing operations). To mitigate damage caused by this differential expansion and contraction (e.g., cracking, solder bridging, etc.), the DTS interconnects 140 and the STPS interconnects 150 may be formed larger and farther apart than DTD interconnects 130, which may experience less thermal stress due to the greater material similarity of the pair of dies 114 on either side of the DTD interconnects. In some embodiments, the DTS interconnects 140 disclosed herein may have a pitch between 10 microns and 250 microns. In some embodiments, the STPS interconnects 150 disclosed herein may have a pitch between 55 microns and 3000 microns, while the DTD interconnects 130 disclosed herein may have a pitch between 5 microns and 120 microns.
The microelectronic assembly 100 of
Although
Many of the elements of the microelectronic assembly 100 of
As shown in
As shown in
The multi-layer die subassembly 104 may include an insulating material 132 (e.g., a dielectric material formed in multiple layers, as known in the art) to form the multiple layers and to embed one or more dies in a layer. In particular, the first die 114-1 and conductive pillars 152 may be surrounded by the insulating material 132 in the first layer 104-1 and, as shown in
The multi-layer die subassembly 104 may have any suitable dimensions. For example, in some embodiments, a thickness of the multi-layer die subassembly 104 may be between 100 um and 2000 um. In some embodiments, the multi-layer die subassembly 104 may include a composite die, such as stacked dies. The multi-layer die subassembly 104 may have any suitable number of layers, any suitable number of dies, and any suitable die arrangement. For example, in some embodiments, the multi-layer die subassembly 104 may have between 3 and 20 layers of dies. In some embodiments, the multi-layer die subassembly 104 may include a layer having between 2 and 50 dies.
In some embodiments, the multi-layer die subassembly 104 may further include a redistribution layer (RDL) (not shown) at a bottom surface 170-2 and/or between the first and second layers 104-1, 104-2. An RDL may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways through the dielectric material (e.g., including conductive traces and/or conductive vias). In some embodiments, the insulating material of the RDL may be composed of dielectric materials, bismaleimide triazine (BT) resin, polyimide materials, epoxy materials (e.g., glass reinforced epoxy matrix materials, epoxy build-up films, or the like), mold materials, oxide-based materials (e.g., silicon dioxide or spin on oxide), or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics).
Although
As shown in
Although
As shown in
Any suitable techniques may be used to manufacture the microelectronic assemblies 100 disclosed herein. For example,
At 604, a surface insulation material 117 may be formed on a top surface of the patterned conductive material, and the surface insulation material 117 may be patterned to form first openings 119A. The first openings 119A in the surface insulation material 117 may be formed by mechanical patterning, laser patterning, dry etch patterning, or lithographic patterning techniques.
At 606, a first photoresist 512-1 may be applied to a top surface of the surface insulation material 117 and lithographically patterning to form second openings 119B.
At 608, a first conductive material, such as copper, may be deposited in the first and second openings 119A, 119B to form a first portion of the N metal layer (e.g., conductive contacts 125, 126 having a first thickness 191), a first material 118 may be deposited on the first conductive material, and the first photoresist may be removed. The first conductive material and the first material 118 may be deposited using any suitable technique, such as electroless plating or electrolytic plating.
At 610, a second photoresist 512-2 may be applied to a top surface of the assembly and lithographically patterned to form third openings 119C.
At 612, a second conductive material, such as copper, may be deposited in the first and third openings 119A, 119C to form a second portion of the N metal layer (e.g., conductive contacts 128, 129 having a second thickness 192), a second material 116 may be deposited on a top surface of the second conductive material, and a first solder 145 may be deposited on a top surface of the second material 116. The second portion of the N metal layer, the second material 116, and the first solder 145 may be deposited using any suitable technique, such as electroless plating or electrolytic plating.
At 614, a third photoresist 512-3 may be applied on the second photoresist 512-2 and lithographically patterned to form fourth openings 119D, a second solder 145 may be deposited on the first solder 145 to increase a thickness (e.g., a z-height) of the first solder 145 at a top surface of conductive contacts 128, and the second and third photoresists 512-2, 512-3 may be removed. The second solder 145 may be deposited using any suitable technique, such as electroless plating or electrolytic plating.
At 616, dies 114-2, 114-3 may be attached to the substrate 107, multi-layer die subassembly 104, or base die 103 by forming DTD interconnects 130 and DTS interconnects 140, where the DTD interconnects 130-1 and DTS interconnects 140-1 include solder 145 having a first thickness 195 and DTD interconnects 130-2 and DTS interconnects 140-2 include solder 145 having a second thickness 197.
At 618, finishing operations may be performed on the bottom surface of the assembly, such as depositing solder resist, depositing solder on a bottom surface (e.g., at the first surface 170-1) of conductive contacts of N−4 metal layer, and coupling to a package substrate 102 via STPS interconnects 150, similar to the microelectronic assembly 100 of
The microelectronic assemblies 100 disclosed herein may be used for any suitable application. For example, in some embodiments, a microelectronic assembly 100 may be used to enable very small form factor voltage regulation for field programmable gate array (FPGA) or processing units (e.g., a central processing unit, a graphics processing unit, a FPGA, a modem, an applications processor, etc.) especially in mobile devices and small form factor devices. In another example, the die 114 in a microelectronic assembly 100 may be a processing device (e.g., a central processing unit, a graphics processing unit, a FPGA, a modem, an applications processor, etc.).
The microelectronic assemblies 100 disclosed herein may be included in any suitable electronic component.
The IC device 1600 may include one or more device layers 1604 disposed on the die substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in
Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 is to be a PMOS or a NMOS transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1602 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1602 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1620 may be formed within the die substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S/D regions 1620 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1602 to form the S/D regions 1620. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1602 may follow the ion-implantation process. In the latter process, the die substrate 1602 may first be etched to form recesses at the locations of the S/D regions 1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1620. In some implementations, the S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1620 may be formed using one or more alternate semiconductor materials such as germanium or a group Ill-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1620.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1640) of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in
The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in
In some embodiments, the interconnect structures 1628 may include lines 1628a and/or vias 1628b filled with an electrically conductive material such as a metal. The lines 1628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1602 upon which the device layer 1604 is formed. For example, the lines 1628a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in
A first interconnect layer 1606 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. The lines 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., the S/D contacts 1624) of the device layer 1604.
A second interconnect layer 1608 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the lines 1628a and the vias 1628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual damascene process) in some embodiments.
A third interconnect layer 1610 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device layer 1604) may be thicker.
The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In
In some embodiments in which the IC device 1600 is a double-sided die (e.g., like the die 114-1), the IC device 1600 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1604. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 1606-1610, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 1604 and additional conductive contacts (not shown) on the opposite side of the IC device 1600 from the conductive contacts 1636.
In other embodiments in which the IC device 1600 is a double-sided die (e.g., like the die 114-1), the IC device 1600 may include one or more TSVs through the die substrate 1602; these TSVs may make contact with the device layer(s) 1604, and may provide conductive pathways between the device layer(s) 1604 and additional conductive contacts (not shown) on the opposite side of the IC device 1600 from the conductive contacts 1636.
In some embodiments, the circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate. In some embodiments the circuit board 1702 may be, for example, a circuit board.
The IC device assembly 1700 illustrated in
The package-on-interposer structure 1736 may include an IC package 1720 coupled to an interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in
In some embodiments, the interposer 1704 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group Ill-V and group IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to TSVs 1706. The interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.
The IC device assembly 1700 illustrated in
Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in
The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMLS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1812 may include multiple communication chips. For instance, a first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications, and a second communication chip 1812 may be dedicated to wired communications.
The electrical device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).
The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the electrical device 1800, as known in the art.
The electrical device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1800 may have any desired form factor, such as a computing device or a hand-held, portable or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server, or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 is a microelectronic assembly, including a substrate having a surface, the surface including: a first conductive contact having a first thickness; and a second conductive contact having a second thickness different than the first thickness, the second conductive contact including a solder material on a top surface; and a bridge component embedded in a dielectric material of the substrate and electrically coupled to the first and second conductive contacts at the surface of the substrate.
Example 2 may include the subject matter of Example 1, and may further specify that the first thickness is greater than the second thickness.
Example 3 may include the subject matter of Examples 1 or 2, and may further specify that the first thickness is between 5 microns and 50 microns.
Example 4 may include the subject matter of any of Examples 1-3, and may further specify that the second thickness is between 2 microns and 35 microns.
Example 5 may include the subject matter of any of Examples 1-4, and may further specify that the first conductive contact includes a first material on a top surface; and wherein the second conductive contact includes a second material between the solder material and the second conductive contact.
Example 6 may include the subject matter of Example 5, and may further specify that the first material includes gold, palladium, nickel, an organic surface protection layer, or a combination thereof.
Example 7 may include the subject matter of Example 5, and may further specify that the second material includes nickel, cobalt, iron, or a combination thereof.
Example 8 may include the subject matter of Example 5, and may further specify that a thickness of the second material is between 1 micron and 8 microns.
Example 9 may include the subject matter of any of Examples 1-8, and may further include a first microelectronic component having a third conductive contact electrically coupled, by a first interconnect, to the first conductive contact, wherein the first interconnect includes solder having a thickness between 2 microns and 35 microns; and a second microelectronic component having a fourth conductive contact electrically coupled, by a second interconnect, to the second conductive contact, wherein the second interconnect includes solder having a thickness between 5 microns and 50 microns.
Example 10 may include the subject matter of Example 9, and may further specify that the first microelectronic component includes memory, a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor.
Example 11 may include the subject matter of Example 9, and may further specify that the bridge component is one of a plurality of bridge components.
Example 12 may include the subject matter of Example 9, and may further specify that the first microelectronic component is one of a plurality of first microelectronic components.
Example 13 may include the subject matter of Example 9, and may further specify that the second microelectronic component is one of a plurality of second microelectronic components.
Example 14 may include the subject matter of Example 9, and may further specify that the surface of the substrate further includes a fifth conductive contact and the first microelectronic component is electrically coupled to the fifth conductive contact, and the microelectronic assembly and may further include a conductive pillar through the dielectric material of the substrate and electrically coupled to the fifth conductive contact.
Example 15 may include the subject matter of any of Examples 1-14, and may further specify that the surface of the substrate is a second surface, the substrate further including a first surface opposite the second surface, and the microelectronic assembly further including a package substrate electrically coupled to the second surface of the substrate.
Example 16 may include the subject matter of any of Examples 1-15, and may further specify that the substrate further includes a core and through core vias.
Example 17 may include the subject matter of any of Examples 1-16, and may further specify that the bridge component includes a first surface and an opposing second surface and is embedded in the dielectric material of the substrate with the second surface electrically coupled to the second and third conductive contacts at the surface of the substrate; and wherein the substrate further includes a conductive material at the first surface of the bridge component.
Example 18 may include the subject matter of Example 17, and may further specify that the substrate further includes an adhesive material between the first surface of the bridge component and the conductive material.
Example 19 is a microelectronic assembly, including a substrate having a surface, the surface including: a first conductive contact having a first thickness; and a second conductive contact having a second thickness different than the first thickness; a first microelectronic component having a third conductive contact electrically coupled, by a first interconnect, to the first conductive contact, wherein the first interconnect includes solder having a thickness between 2 microns and 35 microns; and a second microelectronic component having a fourth conductive contact electrically coupled, by a second interconnect, to the second conductive contact, wherein the second interconnect includes solder having a thickness between 5 microns and 50 microns.
Example 20 may include the subject matter of Example 19, and may further specify that the first thickness is between 5 microns and 50 microns.
Example 21 may include the subject matter of Examples 19 or 20, and may further specify that the second thickness is between 2 microns and 35 microns.
Example 22 may include the subject matter of any of Examples 19-21, and may further include a material between the solder of the second interconnect and the second conductive contact.
Example 23 may include the subject matter of Example 22, and may further specify that the material includes nickel, cobalt, iron, or a combination thereof.
Example 24 may include the subject matter of Example 22, and may further specify that a thickness of the material is between 1 micron and 8 microns.
Example 25 may include the subject matter of any of Examples 19-24, and may further include a bridge component embedded in a dielectric material of the substrate and electrically coupled, by conductive pathways through the substrate, to the first and second conductive contacts at the surface of the substrate.
Example 26 may include the subject matter of any of Examples 19-24, and may further specify that the substrate includes a base die or an interposer.
Example 27 may include the subject matter of any of Examples 19-26, and may further specify that the first microelectronic component includes memory, a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor.
Example 28 may include the subject matter of any of Examples 19-27, and may further specify that the second microelectronic component includes memory, a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor.
Example 29 may include the subject matter of any of Examples 19-28, and may further include a surface insulation material between the surface of the substrate and the first and second conductive contacts.
Example 30 is a microelectronic assembly, including a substrate having a surface, the surface including first conductive contacts and second conductive contacts at a surface of the substrate, wherein the first conductive contacts have a first thickness and the second conductive contacts have a second thickness different than the first thickness; a first microelectronic component having third conductive contacts, wherein respective ones of the third conductive contacts are coupled to respective ones of the first conductive contacts by first interconnects, wherein the first interconnects include solder having a thickness between 2 microns and 35 microns; and a second microelectronic component having fourth conductive contacts, wherein respective ones of the fourth conductive contacts are coupled to respective ones of the second conductive contacts by second interconnects, wherein the second interconnects include solder having a thickness between 5 microns and 50 microns.
Example 31 may include the subject matter of Example 30, and may further specify that the first thickness is greater than the second thickness.
Example 32 may include the subject matter of Examples 30 or 31, and may further specify that the first thickness is between 5 microns and 50 microns.
Example 33 may include the subject matter of any of Examples 30-32, and may further specify that the second thickness is between 2 microns and 35 microns.
Example 34 may include the subject matter of any of Examples 30-33, and may further include a material between the second conductive contacts and the solder of the second interconnects.
Example 35 may include the subject matter of Example 34, and may further specify that the material includes nickel, cobalt, iron, or a combination thereof.
Example 36 may include the subject matter of Example 34, and may further specify that a thickness of the material is between 1 micron and 8 microns.
Example 37 may include the subject matter of any of Examples 30-36, and may further include a surface insulation material between the surface of the substrate and the first and second conductive contacts.
Example 38 may include the subject matter of any of Examples 30-37, and may further include a bridge component embedded in a dielectric material of the substrate and electrically coupled by conductive pathways through the dielectric material of the substrate to some of the first and second conductive contacts at the surface of the substrate.
This invention was made with Government support under Agreement No. HR00111830002 awarded by the United States Department of Defense. The Government has certain rights in the invention.
