Ray Chang

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable delay control for sense amplifiers in a memory
- Patent number 6,385,101
- Issue date May 7, 2002
- Motorola, Inc.
- Ray Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit memory having a fuse detect circuit and method t...
- Patent number 6,157,583
- Issue date Dec 5, 2000
- Motorola, Inc.
- Glenn E. Starnes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable delay control for sense amplifiers in a memory
- Patent number 6,111,796
- Issue date Aug 29, 2000
- Motorola, Inc.
- Ray Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory utilizing a programmable delay to control address buffers
- Patent number 6,108,266
- Issue date Aug 22, 2000
- Motorola, Inc.
- William Robert Weier
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic sense amplifier in a memory capable of limiting the voltage...
- Patent number 6,031,775
- Issue date Feb 29, 2000
- Motorola Inc.
- Ray Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing control of amplifiers in a memory
- Patent number 5,978,286
- Issue date Nov 2, 1999
- Motorola, Inc.
- Ray Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout for noise reduction on a reference voltage
- Patent number 5,670,815
- Issue date Sep 23, 1997
- Motorola, Inc.
- Lawrence F. Childs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Delay locked loop for detecting the phase difference of two signals...
- Patent number 5,610,543
- Issue date Mar 11, 1997
- Motorola Inc.
- Ray Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Power-on reset circuit for preventing multiple word line selections...
- Patent number 5,477,176
- Issue date Dec 19, 1995
- Motorola Inc.
- Ray Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop for detecting the phase difference of two signals...
- Patent number 5,440,515
- Issue date Aug 8, 1995
- Motorola Inc.
- Ray Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Write control for a memory using a delay locked loop
- Patent number 5,440,514
- Issue date Aug 8, 1995
- Motorola Inc.
- Stephen T. Flannagan
- G11 - INFORMATION STORAGE
Information Patent Grant
ECL-to-CMOS buffer having a single-sided delay
- Patent number 5,422,848
- Issue date Jun 6, 1995
- Motorola Inc.
- Kenneth W. Jones
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipelined memory having synchronous and asynchronous operating modes
- Patent number 5,384,737
- Issue date Jan 24, 1995
- Motorola Inc.
- Lawrence F. Childs
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory having a write enable controlled word line
- Patent number 5,268,863
- Issue date Dec 7, 1993
- Motorola, Inc.
- Mark D. Bader
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory having output buffer enable by level comparison and method t...
- Patent number 5,258,951
- Issue date Nov 2, 1993
- Motorola, Inc.
- Ruey J. Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power level converter
- Patent number 5,202,594
- Issue date Apr 13, 1993
- Motorola, Inc.
- Ray Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit memory with improved di/dt control
- Patent number 4,991,140
- Issue date Feb 5, 1991
- Motorola, Inc.
- Karl L. Wang
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Programmable delay control for sense amplifiers in a memory

Integrated circuit memory having a fuse detect circuit and method t...

Programmable delay control for sense amplifiers in a memory

Memory utilizing a programmable delay to control address buffers

Dynamic sense amplifier in a memory capable of limiting the voltage...

Timing control of amplifiers in a memory

Layout for noise reduction on a reference voltage

Delay locked loop for detecting the phase difference of two signals...

Power-on reset circuit for preventing multiple word line selections...

Delay locked loop for detecting the phase difference of two signals...

Write control for a memory using a delay locked loop

ECL-to-CMOS buffer having a single-sided delay

Pipelined memory having synchronous and asynchronous operating modes

Memory having a write enable controlled word line

Memory having output buffer enable by level comparison and method t...

Low power level converter

Integrated circuit memory with improved di/dt control